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    Process for manufacturing semiconductor BICMOS device
    1.
    发明授权
    Process for manufacturing semiconductor BICMOS device 失效
    制造半导体BICMOS器件的工艺

    公开(公告)号：US5462888A

    公开(公告)日：1995-10-31

    申请号：US254223

    申请日：1994-06-06

    申请人： Tzu-Yin Chiu ,  Frank M. Erceg ,  Francis A. Krafty ,  Te-Yin M. Liu ,  William A. Possanza ,  Janmye Sung

    发明人： Tzu-Yin Chiu ,  Frank M. Erceg ,  Francis A. Krafty ,  Te-Yin M. Liu ,  William A. Possanza ,  Janmye Sung

    IPC分类号： H01L21/3213 ,  H01L21/3205 ,  H01L21/762 ,  H01L21/8249 ,  H01L23/52 ,  H01L27/06 ,  H01L21/70

    CPC分类号： H01L21/76229 ,  H01L21/8249 ,  H01L27/0623 ,  Y10S148/106 ,  Y10S148/123 ,  Y10S148/151 ,  Y10S438/926 ,  Y10S438/942

    摘要： A process for fabricating transistors on a substrate is disclosed. In accordance with the process, stacks of material are formed on the surface of the substrate. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. A first layer of polycrystalline material is deposited over the substrate and selectively removed such that only those portions of the polycrystalline layer that surround the stacks of material remain. A layer of silicon nitride or silicon dioxide is then formed over the substrate surface. A first resist is then spun on the substrate surface. This resist aggregates near the stacks of material. An isolation mask is generated that leaves exposed only those areas of the substrate that correspond to the area of overlap between the first polycrystalline area and the stacks of material, which also contain a layer of polycrystalline material. The substrate is then subjected to an etchback process to remove the portion of the polysilicon material that overlaps the material in the stacks.

    摘要翻译： 公开了一种在衬底上制造晶体管的工艺。 根据该方法，在基板的表面上形成堆叠的材料。 在堆叠周围产生二氧化硅壁，以便将堆叠内的材料与沉积在壁外部的材料隔离。 第一层多晶材料沉积在衬底上并选择性地去除，使得只有围绕堆叠材料的多晶层的那些部分保留。 然后在衬底表面上形成一层氮化硅或二氧化硅。 然后在衬底表面上旋转第一抗蚀剂。 该抗蚀剂聚集在材料堆附近。 产生隔离掩模，其仅露出对应于第一多晶区域和也包含多晶材料层的材料堆叠之间的重叠区域的基板的那些区域。 然后对衬底进行回蚀处理以去除与堆叠中的材料重叠的多晶硅材料的部分。

    Process for manufacturing semiconductor BICMOS device
    3.
    发明授权
    Process for manufacturing semiconductor BICMOS device 失效
    制造半导体BICMOS器件的工艺

    公开(公告)号：US4824796A

    公开(公告)日：1989-04-25

    申请号：US77953

    申请日：1987-07-10

    申请人： Tzu-Yin Chiu ,  Gen M. Chin ,  Ronald C. Hanson ,  Maureen Y. Lau ,  Kwing F. Lee ,  Mark D. Morris ,  Alexander M. Voshchenkov ,  Avinoam Kornblit ,  Joseph Lebowitz ,  William T. Lynch

    发明人： Tzu-Yin Chiu ,  Gen M. Chin ,  Ronald C. Hanson ,  Maureen Y. Lau ,  Kwing F. Lee ,  Mark D. Morris ,  Alexander M. Voshchenkov ,  Avinoam Kornblit ,  Joseph Lebowitz ,  William T. Lynch

    IPC分类号： H01L29/73 ,  H01L21/225 ,  H01L21/3215 ,  H01L21/331 ,  H01L21/82 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L29/41783 ,  H01L21/2257 ,  H01L21/32155 ,  H01L21/8249 ,  H01L27/0623 ,  Y10S148/009 ,  Y10S148/01 ,  Y10S148/124 ,  Y10S148/151

    摘要： A process for creating bipolar and CMOS transistors on a p-type silicon substrate is disclosed. The silicon substrate has typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer in contact with the epitaxial layer. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon in contact with the epitaxial layer is deposited outside the walls surrounding the stacks. All polycrystalline silicon layers in contact with the epitaxial layer are implanted with appropriate dopants such that these layers serve as reservoirs of dopant in order to simultaneously create the source and drain elements of the CMOS devices and the emitter elements of the bipolar devices during a heating step in the process. A tungsten layer is deposited over the polycrystalline layer in order to provide a conductive coupling to aluminum electrodes.

    摘要翻译： 公开了一种在p型硅衬底上制造双极和CMOS晶体管的工艺。 硅衬底具有典型的n +掩埋阱和场氧化物区域以隔离各个晶体管器件。 根据该过程，在CMOS器件的栅极元件和双极晶体管的发射极元件之上形成材料堆叠。 在栅极元件上的堆叠材料具有与衬底的外延层接触的二氧化硅栅极层，并且在发射极元件上的材料堆叠具有与外延层接触的多晶硅层。 在堆叠周围产生二氧化硅壁，以便将堆叠内的材料与沉积在壁外部的材料隔离。 与外延层接触的多晶硅沉积在堆叠周围的壁的外部。 与外延层接触的所有多晶硅层都注入合适的掺杂剂，使得这些层用作掺杂剂的储存器，以便在加热步骤期间同时产生CMOS器件的源极和漏极元件以及双极器件的发射极元件 正在进行中。 为了提供与铝电极的导电耦合，在多晶层上沉积钨层。

    Process for manufacturing semiconductor BICMOS device
    4.
    发明授权
    Process for manufacturing semiconductor BICMOS device 失效
    制造半导体BICMOS器件的工艺

    公开(公告)号：US4784971A

    公开(公告)日：1988-11-15

    申请号：US47946

    申请日：1987-05-08

    申请人： Tzu-Yin Chiu ,  Gen M. Chin ,  Ronald. C. Hanson ,  Maureen Y. Lau ,  Kwing F. Lee ,  Mark D. Morris ,  Alexander M. Voschenkov

    发明人： Tzu-Yin Chiu ,  Gen M. Chin ,  Ronald. C. Hanson ,  Maureen Y. Lau ,  Kwing F. Lee ,  Mark D. Morris ,  Alexander M. Voschenkov

    IPC分类号： H01L29/73 ,  H01L21/225 ,  H01L21/3215 ,  H01L21/331 ,  H01L21/82 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L29/41783 ,  H01L21/2257 ,  H01L21/32155 ,  H01L21/8249 ,  H01L27/0623 ,  Y10S148/009 ,  Y10S148/01 ,  Y10S148/124 ,  Y10S148/151

    摘要： A process for creating bipolar and CMOS transistors on a p-type silicon substrate is disclosed. The silicon substrate has a typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer in contact with the epitaxial layer. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon in contact with the epitaxial layer is deposited outside the walls surrounding the stacks. All polycrystalline silicon layers in contact with the epitaxial layer are implanted with appropriate dopants such that these layers serve as reservoirs of dopant in order to simultaneously create the source and drain elements of the CMOS devices and the emitter elements of the bipolar device during a heating step in the process. A tungsten layer is deposited over the polycrystalline layer in order to provide a conductive coupling to aluminum electrodes.

    摘要翻译： 公开了一种在p型硅衬底上制造双极和CMOS晶体管的工艺。 硅衬底具有典型的n +掩埋阱和场氧化物区域以隔离各个晶体管器件。 根据该过程，在CMOS器件的栅极元件和双极晶体管的发射极元件之上形成材料堆叠。 在栅极元件上的堆叠材料具有与衬底的外延层接触的二氧化硅栅极层，并且在发射极元件上的材料堆叠具有与外延层接触的多晶硅层。 在堆叠周围产生二氧化硅壁，以便将堆叠内的材料与沉积在壁外部的材料隔离。 与外延层接触的多晶硅沉积在堆叠周围的壁的外部。 与外延层接触的所有多晶硅层都注入合适的掺杂剂，使得这些层用作掺杂剂的储存器，以便在加热步骤期间同时产生CMOS器件的源极和漏极元件以及双极器件的发射极元件 正在进行中。 为了提供与铝电极的导电耦合，在多晶层上沉积钨层。

    Process of manufacturing a high frequency bipolar transistor utilizing doped silicide with self-aligned masking
    5.
    发明授权
    Process of manufacturing a high frequency bipolar transistor utilizing doped silicide with self-aligned masking 失效
    使用具有自对准掩蔽的掺杂硅化物制造高频双极晶体管的工艺

    公开(公告)号：US4586968A

    公开(公告)日：1986-05-06

    申请号：US628408

    申请日：1984-07-06

    申请人： Augustin Coello-Vera

    发明人： Augustin Coello-Vera

    IPC分类号： H01L29/73 ,  H01L21/033 ,  H01L21/225 ,  H01L21/331 ,  H01L21/60 ,  H01L29/41 ,  H01L29/732 ,  H01L21/283

    CPC分类号： H01L21/76897 ,  H01L21/0337 ,  H01L21/2257 ,  H01L29/41 ,  H01L29/66303 ,  Y10S148/019 ,  Y10S148/02 ,  Y10S148/106 ,  Y10S148/151

    摘要： Apart from the base fingers (10), this transistor includes a titanium silicide coating, from which the base diffusions have been formed, and a silicon nitride coating (4). The edges of sandwiches made up of bands (3) and (4) are bordered by a silica bank (7) formed automatically by deposit and anisotropic attack, without additional masking. The emitter fingers (9) are overhung by a polycrystalline silicon layer (8) from which doping of these fingers has been obtained.The possibility is also obtained, automatically and without masks alignment, of having the emitter and base fingers brought firmly together with minimum protection distances.

    摘要翻译： 除了基底指（10）之外，该晶体管还包括已形成基极扩散的硅化钛涂层和氮化硅涂层（4）。 由条带（3）和（4）组成的三明治边缘是由沉积和各向异性攻击自动形成的二氧化硅银（7）边界，无需额外掩蔽。 发射极指（9）被多晶硅层（8）覆盖，从中可以获得这些指状物的掺杂。 也可以自动地且没有掩模对准的可能性，使发射器和基部手指以最小的保护距离牢固地连接在一起。

    Negative-resistance semiconductor device
    6.
    发明授权
    Negative-resistance semiconductor device 失效
    负电阻半导体器件

    公开(公告)号：US4064525A

    公开(公告)日：1977-12-20

    申请号：US696389

    申请日：1976-06-15

    申请人： Gota Kano ,  Naoyuki Tsuda ,  Hitoo Iwasa

    发明人： Gota Kano ,  Naoyuki Tsuda ,  Hitoo Iwasa

    IPC分类号： H01L29/78 ,  G05F3/24 ,  H01L21/331 ,  H01L21/337 ,  H01L21/822 ,  H01L27/04 ,  H01L27/098 ,  H01L29/73 ,  H01L29/80 ,  H01L29/808 ,  H01L29/86 ,  H03H11/52 ,  H01L27/02

    CPC分类号： H01L27/098 ,  H03H11/52 ,  Y10S148/018 ,  Y10S148/049 ,  Y10S148/151

    摘要： A pair of field-effect transistors (hereinafter referred to as FETs) of p-channel type and n-channel type, respectively, both to be electrically actuated in a depletion mode, are formed on a single semiconductor substrate, for instance, a single silicon substrate, and both sources or both drains are connected to each other, or the source of one FET and the drain of the other FET are connected to each other, whereby the pair of FETs are series-connected, and the gate electrode of each FET is connected to the drain electrode or the source electrode that is not series connected in the abovementioned way, respectively, of the other FET. When a voltage of specified range is applied across both non-series-connected electrodes, i.e., the two external terminals, the resulting voltage-current characteristic presents a so-called dynatron-type characteristic, producing a negative-resistance phenomenon over a fairly wide range of applied voltage.Since this device is, as seen from outside as one device, a two-terminal device constituted on a single substrate, it is not only fit to be highly integrated, but also able to produce a state of virtually zero value of cut-off current. Consequently, this device can be utilized for switching, memorization, large amplitude oscillation, and other various uses.

    摘要翻译： 在单个半导体衬底上形成分别以耗尽模式电致动的p沟道型和n沟道型的一对场效应晶体管（以下称为FET），例如单个 硅衬底，两个源极或两个漏极彼此连接，或者一个FET的源极和另一个FET的漏极彼此连接，由此一对FET串联连接，并且每个FET的栅极电极 FET分别与另一个FET分别以上述方式串联的漏电极或源极连接。 当在两个非串联电极（即两个外部端子）上施加规定范围的电压时，所得到的电压 - 电流特性呈现所谓的电压特性，在相当宽的范围内产生负电阻现象 施加电压范围。

    Transistor having an emitter with a low impurity concentration portion and a high impurity concentration portion
    9.
    发明授权
    Transistor having an emitter with a low impurity concentration portion and a high impurity concentration portion 失效
    晶体管具有具有低杂质浓度部分和高杂质浓度部分的发射极

    公开(公告)号：US4007474A

    公开(公告)日：1977-02-08

    申请号：US561914

    申请日：1975-03-25

    申请人： Hajime Yagi ,  Tadaharu Tsuyuki

    发明人： Hajime Yagi ,  Tadaharu Tsuyuki

    IPC分类号： H01L27/082 ,  H01L29/08 ,  H01L29/72 ,  H01L27/02 ,  H01L29/00

    CPC分类号： H01L29/0804 ,  H01L27/0826 ,  H01L29/0839 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/151 ,  Y10S148/157

    摘要： A semiconductor device having a high current amplification gain which includes a low impurity concentration in the emitter region of the device, an injected minority carrier diffusion length L greater than the width of the emitter, and a high impurity concentration region of the same type as the emitter overlying at least a portion of said emitter region which provides a built-in-field where there is a drift current of minority carriers back toward the base region. The built-in field is larger than kT(qL) so that the drift current adjacent the built-in-field substantially cancels the minority carrier diffusion current injected from the base region.

    摘要翻译： 具有高电流放大增益的半导体器件，其包括在器件的发射极区域中的低杂质浓度，大于发射极宽度的注入的少数载流子扩散长度L和与该发射极的相同类型的高杂质浓度区域 发射极覆盖所述发射极区域的至少一部分，其提供内部场，其中少数载流子的漂移电流返回到基极区域。 内置场大于kT（qL），使得与内置场相邻的漂移电流基本上抵消从基极区域注入的少数载流子扩散电流。