公开(公告)号：US20090218655A1

公开(公告)日：2009-09-03

申请号：US12387706

申请日：2009-05-06

申请人： Yinon Degani ,  Maureen Y. Lau ,  King Lien Tai

发明人： Yinon Degani ,  Maureen Y. Lau ,  King Lien Tai

IPC分类号： H01L27/06 ,  B32B9/04

CPC分类号： H01L28/40 ,  H01L27/016 ,  H01L27/101 ,  H01L28/10 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： The specification describes an integrated passive device (IPD) that is formed on a polysilicon substrate. A method for making the IPD is disclosed wherein the polysilicon substrate is produced starting with a single crystal handle wafer, depositing a thick substrate layer of polysilicon on one or both sides of the starting wafer, forming the IPD on one of the polysilicon substrate layers, and removing the handle wafer. In a preferred embodiment the single crystal silicon handle wafer is a silicon wafer rejected from a single crystal silicon wafer production line.

摘要翻译： 本说明书描述了形成在多晶硅衬底上的集成无源器件（IPD）。 公开了一种用于制造IPD的方法，其中从单晶晶片处开始制造多晶硅衬底，在起始晶片的一侧或两侧沉积厚的多晶硅衬底层，在多晶硅衬底层之一上形成IPD， 并移除手柄晶片。 在优选实施例中，单晶硅处理晶片是从单晶硅晶片生产线排除的硅晶片。

公开(公告)号：US5481205A

公开(公告)日：1996-01-02

申请号：US344393

申请日：1994-11-23

申请人： Robert C. Frye ,  Maureen Y. Lau ,  King L. Tai

发明人： Robert C. Frye ,  Maureen Y. Lau ,  King L. Tai

IPC分类号： H01L21/66 ,  G01R1/067 ,  G01R1/073 ,  G01R31/26 ,  H01L27/10 ,  H05K3/32 ,  G01R1/06 ,  H01L23/48

CPC分类号： H05K3/325 ,  G01R1/07307 ,  G01R1/06738 ,  H01L2924/0002

摘要： A given testing substrate for fast-testing many integrated-circuit electronic devices, one after the other, has a set of mutually insulated collated wiring areas that can be aligned with solder-bump I/O pads of the electronic devices. At the surface of each of the corrugated areas is located a layer that is an electrically conductive durable oxide, or that is itself durable, electrically conductive, and non-oxidizable. During testing, the solder-bump I/O pads of the electronic device being tested are aligned with and pressed against the corrugated wiring areas of the given substrate. Alternatively, the electronic devices being of the electrically programmable variety, such as EPROMs, programming voltages can be delivered to each of the devices, one after the other, through the corrugated wiring areas of a single substrate.

摘要翻译： 给定的用于快速测试许多集成电路电子器件的测试基板，一个接一个地具有一组可以与电子器件的焊料凸块I / O焊盘对准的相互绝缘的整理布线区域。 在每个波纹区域的表面上设置有导电耐用氧化物的层，或者其本身是耐用的，导电的和不可氧化的。 在测试期间，正在测试的电子器件的焊料凸块I / O焊盘与给定衬底的波纹布线区域对准并压紧。 或者，可以通过单个基板的波纹布线区域，一个接一个地将诸如EPROM的编程电压的电可编程品种的电子装置传送到每个装置。

公开(公告)号：US4824796A

公开(公告)日：1989-04-25

申请号：US77953

申请日：1987-07-10

申请人： Tzu-Yin Chiu ,  Gen M. Chin ,  Ronald C. Hanson ,  Maureen Y. Lau ,  Kwing F. Lee ,  Mark D. Morris ,  Alexander M. Voshchenkov ,  Avinoam Kornblit ,  Joseph Lebowitz ,  William T. Lynch

发明人： Tzu-Yin Chiu ,  Gen M. Chin ,  Ronald C. Hanson ,  Maureen Y. Lau ,  Kwing F. Lee ,  Mark D. Morris ,  Alexander M. Voshchenkov ,  Avinoam Kornblit ,  Joseph Lebowitz ,  William T. Lynch

IPC分类号： H01L29/73 ,  H01L21/225 ,  H01L21/3215 ,  H01L21/331 ,  H01L21/82 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L29/41783 ,  H01L21/2257 ,  H01L21/32155 ,  H01L21/8249 ,  H01L27/0623 ,  Y10S148/009 ,  Y10S148/01 ,  Y10S148/124 ,  Y10S148/151

摘要： A process for creating bipolar and CMOS transistors on a p-type silicon substrate is disclosed. The silicon substrate has typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer in contact with the epitaxial layer. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon in contact with the epitaxial layer is deposited outside the walls surrounding the stacks. All polycrystalline silicon layers in contact with the epitaxial layer are implanted with appropriate dopants such that these layers serve as reservoirs of dopant in order to simultaneously create the source and drain elements of the CMOS devices and the emitter elements of the bipolar devices during a heating step in the process. A tungsten layer is deposited over the polycrystalline layer in order to provide a conductive coupling to aluminum electrodes.

摘要翻译： 公开了一种在p型硅衬底上制造双极和CMOS晶体管的工艺。 硅衬底具有典型的n +掩埋阱和场氧化物区域以隔离各个晶体管器件。 根据该过程，在CMOS器件的栅极元件和双极晶体管的发射极元件之上形成材料堆叠。 在栅极元件上的堆叠材料具有与衬底的外延层接触的二氧化硅栅极层，并且在发射极元件上的材料堆叠具有与外延层接触的多晶硅层。 在堆叠周围产生二氧化硅壁，以便将堆叠内的材料与沉积在壁外部的材料隔离。 与外延层接触的多晶硅沉积在堆叠周围的壁的外部。 与外延层接触的所有多晶硅层都注入合适的掺杂剂，使得这些层用作掺杂剂的储存器，以便在加热步骤期间同时产生CMOS器件的源极和漏极元件以及双极器件的发射极元件 正在进行中。 为了提供与铝电极的导电耦合，在多晶层上沉积钨层。

公开(公告)号：US4784971A

公开(公告)日：1988-11-15

申请号：US47946

申请日：1987-05-08

申请人： Tzu-Yin Chiu ,  Gen M. Chin ,  Ronald. C. Hanson ,  Maureen Y. Lau ,  Kwing F. Lee ,  Mark D. Morris ,  Alexander M. Voschenkov

发明人： Tzu-Yin Chiu ,  Gen M. Chin ,  Ronald. C. Hanson ,  Maureen Y. Lau ,  Kwing F. Lee ,  Mark D. Morris ,  Alexander M. Voschenkov

IPC分类号： H01L29/73 ,  H01L21/225 ,  H01L21/3215 ,  H01L21/331 ,  H01L21/82 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L29/41783 ,  H01L21/2257 ,  H01L21/32155 ,  H01L21/8249 ,  H01L27/0623 ,  Y10S148/009 ,  Y10S148/01 ,  Y10S148/124 ,  Y10S148/151

摘要： A process for creating bipolar and CMOS transistors on a p-type silicon substrate is disclosed. The silicon substrate has a typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer in contact with the epitaxial layer. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon in contact with the epitaxial layer is deposited outside the walls surrounding the stacks. All polycrystalline silicon layers in contact with the epitaxial layer are implanted with appropriate dopants such that these layers serve as reservoirs of dopant in order to simultaneously create the source and drain elements of the CMOS devices and the emitter elements of the bipolar device during a heating step in the process. A tungsten layer is deposited over the polycrystalline layer in order to provide a conductive coupling to aluminum electrodes.

摘要翻译： 公开了一种在p型硅衬底上制造双极和CMOS晶体管的工艺。 硅衬底具有典型的n +掩埋阱和场氧化物区域以隔离各个晶体管器件。 根据该过程，在CMOS器件的栅极元件和双极晶体管的发射极元件之上形成材料堆叠。 在栅极元件上的堆叠材料具有与衬底的外延层接触的二氧化硅栅极层，并且在发射极元件上的材料堆叠具有与外延层接触的多晶硅层。 在堆叠周围产生二氧化硅壁，以便将堆叠内的材料与沉积在壁外部的材料隔离。 与外延层接触的多晶硅沉积在堆叠周围的壁的外部。 与外延层接触的所有多晶硅层都注入合适的掺杂剂，使得这些层用作掺杂剂的储存器，以便在加热步骤期间同时产生CMOS器件的源极和漏极元件以及双极器件的发射极元件 正在进行中。 为了提供与铝电极的导电耦合，在多晶层上沉积钨层。

公开(公告)号：US07259077B2

公开(公告)日：2007-08-21

申请号：US10835338

申请日：2004-04-29

申请人： Yinon Degani ,  Maureen Y. Lau ,  King Lien Tai

发明人： Yinon Degani ,  Maureen Y. Lau ,  King Lien Tai

IPC分类号： H01L21/20

CPC分类号： H01L28/40 ,  H01L27/016 ,  H01L27/101 ,  H01L28/10 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： The specification describes an integrated passive device (IPD) that is formed on a polysilicon substrate. A method for making the IPD is disclosed wherein the polysilicon substrate is produced starting with a single crystal handle wafer, depositing a thick substrate layer of polysilicon on one or both sides of the starting wafer, forming the IPD on one of the polysilicon substrate layers, and removing the handle wafer. In a preferred embodiment the single crystal silicon handle wafer is a silicon wafer rejected from a single crystal silicon wafer production line.