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    Temporary connections for fast electrical access to electronic devices
    1.
    发明授权
    Temporary connections for fast electrical access to electronic devices 失效
    用于快速电气接入电子设备的临时连接

    公开(公告)号：US5481205A

    公开(公告)日：1996-01-02

    申请号：US344393

    申请日：1994-11-23

    Applicant: Robert C. Frye ,  Maureen Y. Lau ,  King L. Tai

    Inventor： Robert C. Frye ,  Maureen Y. Lau ,  King L. Tai

    IPC: H01L21/66 ,  G01R1/067 ,  G01R1/073 ,  G01R31/26 ,  H01L27/10 ,  H05K3/32 ,  G01R1/06 ,  H01L23/48

    CPC classification number: H05K3/325 ,  G01R1/07307 ,  G01R1/06738 ,  H01L2924/0002

    Abstract: A given testing substrate for fast-testing many integrated-circuit electronic devices, one after the other, has a set of mutually insulated collated wiring areas that can be aligned with solder-bump I/O pads of the electronic devices. At the surface of each of the corrugated areas is located a layer that is an electrically conductive durable oxide, or that is itself durable, electrically conductive, and non-oxidizable. During testing, the solder-bump I/O pads of the electronic device being tested are aligned with and pressed against the corrugated wiring areas of the given substrate. Alternatively, the electronic devices being of the electrically programmable variety, such as EPROMs, programming voltages can be delivered to each of the devices, one after the other, through the corrugated wiring areas of a single substrate.

    Abstract translation: 给定的用于快速测试许多集成电路电子器件的测试基板，一个接一个地具有一组可以与电子器件的焊料凸块I / O焊盘对准的相互绝缘的整理布线区域。 在每个波纹区域的表面上设置有导电耐用氧化物的层，或者其本身是耐用的，导电的和不可氧化的。 在测试期间，正在测试的电子器件的焊料凸块I / O焊盘与给定衬底的波纹布线区域对准并压紧。 或者，可以通过单个基板的波纹布线区域，一个接一个地将诸如EPROM的编程电压的电可编程品种的电子装置传送到每个装置。

    Interconnection lines for wafer-scale-integrated assemblies
    2.
    发明授权
    Interconnection lines for wafer-scale-integrated assemblies 失效
    用于晶片级集成组件的互连线

    公开(公告)号：US4703288A

    公开(公告)日：1987-10-27

    申请号：US719533

    申请日：1985-04-03

    Applicant: Robert C. Frye ,  King L. Tai

    Inventor： Robert C. Frye ,  King L. Tai

    IPC: H01L21/822 ,  H01L21/3205 ,  H01L23/52 ,  H01L23/538 ,  H01L23/66 ,  H01L27/04 ,  H01P3/08

    CPC classification number: H01L23/538 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011

    Abstract: In wafer-scale-integrated assemblies, microminiature transmission lines are utilized as interconnects on the wafer. The extremely small cross-sectional area of a typical such line results in its total line resistance being relatively large. Such a line exhibits signal reflections and resonances. In practice, it is not feasible to eliminate these effects by conventional load termination techniques. As a result, the frequency at which digital signals can be transmitted over such a line is typically limited to well below its so-called resonance limit. In accordance with a feature of the invention, the structural parameters of each line are selected to meet specified design criteria that ensure optimal high-frequency performance of the line.

    Abstract translation: 在晶片级集成组件中，微型传输线被用作晶片上的互连。 典型的这种线的极小的横截面积导致其总线路电阻相对较大。 这样一条线表现出信号反射和谐振。 在实践中，通过传统的负载终止技术消除这些影响是不可行的。 结果，数字信号可以通过这种线传输的频率通常被限制在远远低于其所谓的共振极限。 根据本发明的特征，选择每条线的结构参数以满足确保线路的最佳高频性能的规定设计标准。

    Multi-chip modules having chip-to-chip interconnections with reduced signal voltage level and swing
    3.
    发明授权
    Multi-chip modules having chip-to-chip interconnections with reduced signal voltage level and swing 失效
    具有芯片到芯片互连的多芯片模块具有降低的信号电压电平和摆幅

    公开(公告)号：US5461333A

    公开(公告)日：1995-10-24

    申请号：US200986

    申请日：1994-02-24

    Applicant: Joseph H. Condon ,  Robert C. Frye ,  Thaddeus J. Gabara ,  King L. Tai ,  Scott C. Knauer, deceased ,  Carroll H. Knauer, executor

    Inventor： Joseph H. Condon ,  Robert C. Frye ,  Thaddeus J. Gabara ,  King L. Tai ,  Scott C. Knauer, deceased ,  Carroll H. Knauer, executor

    IPC: H03K3/012 ,  H03K3/356 ,  H03K17/10 ,  H03K17/687

    CPC classification number: H01L25/0655 ,  H03K3/012 ,  H03K3/356052 ,  H03K3/356147 ,  H01L2224/16225 ,  H01L2924/13091

    Abstract: A multi-chip module is composed of two or more integrated-circuit chips located on a substrate such as a dielectrically coated silicon substrate. The chips are interconnected by means of transmission wiring lines. At least some of the chips contain one or more input buffer circuits, each composed of two branches ("legs"). Each such branch contains, in one embodiment, an n-channel MOS transistor connected in series with a pair of series-connected p-channel MOS transistors--whereby, in each such branch, one of the p-channel MOS transistors is located between (intermediate) the other of the p-channel MOS transistors and the n-channel MOS transistor of that same branch. On the other hand, in each buffer circuit, the intermediate p-channel MOS transistors of both branches are cross-coupled. Each of the n-channel MOS transistors is connected in a common gate configuration to receive one of the complementary input signals coming from the transmission wiring lines, and the other of the p-channel transistors in each branch is connected in a common source configuration to receive the other of the complementary input signals.

    Abstract translation: 多芯片模块由位于诸如介电涂覆的硅衬底的衬底上的两个或多个集成电路芯片组成。 芯片通过传输线路相互连接。 至少一些芯片包含一个或多个输入缓冲器电路，每个由两个分支（“支脚”）组成。 每个这样的分支在一个实施例中包含与一对串联连接的p沟道MOS晶体管串联连接的n沟道MOS晶体管，由此在每个这样的分支中，一个p沟道MOS晶体管位于（ 中间）另一个p沟道MOS晶体管和同一分支的n沟道MOS晶体管。 另一方面，在每个缓冲电路中，两个分支的中间p沟道MOS晶体管是交叉耦合的。 每个n沟道MOS晶体管以公共栅极配置连接以接收来自传输布线的互补输入信号之一，并且每个分支中的另一个p沟道晶体管以公共源配置连接到 接收另一个互补输入信号。

    Method for making multichip circuits using active semiconductor substrates
    4.
    发明授权
    Method for making multichip circuits using active semiconductor substrates 失效
    使用有源半导体衬底制造多芯片电路的方法

    公开(公告)号：US5534465A

    公开(公告)日：1996-07-09

    申请号：US370902

    申请日：1995-01-10

    Applicant: Robert C. Frye ,  King L. Tai

    Inventor： Robert C. Frye ,  King L. Tai

    IPC: H01L25/065 ,  H01L21/60

    CPC classification number: H01L25/0657 ,  H01L2224/16 ,  H01L2225/06527 ,  H01L2225/06586 ,  H01L2924/1305

    Abstract: In accordance with the invention, a multichip circuit is fabricated by providing an active semiconductor substrate comprising a set of isolated components including active components such as transistors, forming on a surface of the substrate a plurality of paths incorporating components from the substrate for interconnecting a plurality integrated circuit devices, and mounting the ICs on the surface in contact with their respectively appropriate paths. The preferred active substrate is similar in structure to a silicon integrated circuit except that the circuit components are interconnected only by the paths interconnecting the ICs. Advantageously the ICs are surface mounted on the substrate.

    Abstract translation: 根据本发明，通过提供一种有源半导体衬底来制造多芯片电路，所述有源半导体衬底包括一组隔离组件，所述有源半导体衬底包括诸如晶体管的有源器件，在衬底的表面上形成多个通路， 集成电路器件，并将IC安装在与其相应适当路径接触的表面上。 优选的有源衬底在结构上类似于硅集成电路，除了电路部件仅通过互连IC的路径互连。 有利地，IC表面安装在基板上。

    Optical fiber switch
    7.
    发明授权
    Optical fiber switch 失效
    光纤开关

    公开(公告)号：US5000532A

    公开(公告)日：1991-03-19

    申请号：US431941

    申请日：1989-11-06

    Applicant: Richard T. Kraetsch ,  Richard J. Pimpinella ,  Leonard W. Schaper ,  King L. Tai

    Inventor： Richard T. Kraetsch ,  Richard J. Pimpinella ,  Leonard W. Schaper ,  King L. Tai

    IPC: G02B6/35 ,  G02B6/36

    CPC classification number: G02B6/3508 ,  G02B6/355 ,  G02B6/3572 ,  G02B6/3582 ,  G02B6/3652 ,  G02B6/3692

    Abstract: A precisely aligned optical fiber switch assembly. A base member has a vee groove for supporting a fixed optical fiber and a second optical fiber in optical alignment with the fixed fiber. The groove contains sections of different dimensions that receive and align sheathed portions of the fibers and groove sections that receive and align unsheathed portions of the fibers. First aligning means on the base member longitudinally position the fixed and second fibers in the groove. Covering means mate with the base member for covering at least part of the sheathed portions of the fibers. Aligning means position the covering means precisely with respect to the base member.

    Abstract translation: 精密对准的光纤开关组件。 基座构件具有用于支撑固定光纤的vee槽和与固定光纤对准的第二光纤。 凹槽包含不同尺寸的部分，其接收和对准纤维的护套部分和容纳和对准纤维未固化部分的凹槽部分。 基体上的第一对准装置将固定和第二纤维纵向定位在槽中。 覆盖装置与基部构件配合以覆盖纤维的至少一部分护套部分。 对准装置将覆盖装置相对于基座构件精确地定位。

    Method for fabricating devices with DC bias-controlled reactive ion etching
    10.
    发明授权
    Method for fabricating devices with DC bias-controlled reactive ion etching 失效
    用直流偏置控制反应离子蚀刻制造器件的方法

    公开(公告)号：US4496448A

    公开(公告)日：1985-01-29

    申请号：US541459

    申请日：1983-10-13

    Applicant: King L. Tai ,  Frederick Vratny

    Inventor： King L. Tai ,  Frederick Vratny

    IPC: H01L21/302 ,  H01J37/32 ,  H01L21/3065 ,  C23C15/00

    CPC classification number: H01J37/32174 ,  H01J37/32082 ,  H01J37/3299 ,  H01J2237/3341 ,  H01J2237/3345

    Abstract: A method and apparatus for fabricating a device is disclosed, which method involves a new reactive ion etching technique. Both a high etch rate and, for example, a high etch selectivity are simultaneously achieved with the inventive reactive ion etching technique by discharging an electrode of the reactive ion etching apparatus in response to a preselected criterion, e.g., a magnitude of a DC bias at said electrode which equals, or exceeds, a preselected value.

    Abstract translation: 公开了一种用于制造器件的方法和装置，该方法包括新的反应离子蚀刻技术。 通过本发明的反应离子蚀刻技术，通过根据预先选择的标准放电反应离子蚀刻设备的电极，例如，高的蚀刻速率和例如高的蚀刻选择性 所述电极等于或超过预选值。

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