公开(公告)号：US4065680A

公开(公告)日：1977-12-27

申请号：US685503

申请日：1976-05-12

申请人： Lewis K. Russell

发明人： Lewis K. Russell

IPC分类号： H03K3/037 ,  H03K17/60 ,  H03K17/66 ,  H03K19/018 ,  H03K19/091 ,  H03K19/21 ,  H03K19/40

CPC分类号： H03K17/66 ,  H03K17/60 ,  H03K19/01818 ,  H03K19/091 ,  H03K19/212 ,  H03K3/037

摘要： Unidirectional and bidirectional bipolar logic transmission gates have an input, an output, a gate control, supply and common terminals. The unilateral transmission gate circuit includes first and second switching transistors and associated first and second source tranisistors. The transistors each have collector, base and emitter electrodes, said first source transistor emitter being connected to said supply terminal. The collector of the first switching transistor is connected to the base of the second switching transistor and defines a gate logic node. The base of the first switching transistor is connected to the first input terminal and the collector of the second switching transistor is connected to the output terminal with both switching transistor emitters being connected to the common terminal. Gate switching means is connected between said gate logic node and said gate control input, said means being responsive to first and second logic levels at said gate control input for driving said gate logic node to first and second states causing the transmission gate to assume open and closed states from input to output. A bidirectional bipolar logic transmission gate includes an additional gate logic node and gate switching means simultaneously drives said gate logic node and additional gate logic node to first and second states causing the transmission gate to assume bilateral open and closed states between said first and second input and output terminals.

摘要翻译： 单向和双向双极逻辑传输门具有输入，输出，门控制，电源和公共端。 单向传输门电路包括第一和第二开关晶体管及相关的第一和第二源极电阻。 晶体管各自具有集电极，基极和发射极，所述第一源晶体管发射极连接到所述电源端。 第一开关晶体管的集电极连接到第二开关晶体管的基极并限定栅极逻辑节点。 第一开关晶体管的基极连接到第一输入端子，并且第二开关晶体管的集电极连接到输出端子，两个开关晶体管发射极连接到公共端子。 门切换装置连接在所述门逻辑节点和所述门控制输入之间，所述装置响应于所述门控制输入处的第一和第二逻辑电平，用于将所述门逻辑节点驱动为导致传输门呈开状态的第一状态和第二状态， 关闭状态从输入到输出。 双向双极逻辑传输门包括附加的门逻辑节点和门切换装置，同时将所述门逻辑节点和附加门逻辑节点驱动到第一和第二状态，导致传输门在所述第一和第二输入之间呈现双向打开和关闭状态; 输出端子。

公开(公告)号：US4140920A

公开(公告)日：1979-02-20

申请号：US896880

申请日：1978-04-17

申请人： Tich T. Dao ,  Lewis K. Russell ,  Edward J. McCluskey

发明人： Tich T. Dao ,  Lewis K. Russell ,  Edward J. McCluskey

IPC分类号： G06F7/49 ,  H03K5/15 ,  H03K19/08 ,  H03K19/091 ,  H03K19/23 ,  G06F7/50 ,  H03K19/20

CPC分类号： G06F7/49 ,  H03K19/0813 ,  H03K19/091 ,  H03K19/0917 ,  H03K19/23 ,  H03K5/15013

摘要： Logic circuitry provides predetermined logic outputs in response to logical combinations of inputs. The circuitry includes a plurality of input devices for receiving logic inputs and capable of assuming conduction states in response to the logic levels of said inputs. At least one output device is connected to two or more input devices. Means having predetermined logic levels is provided connected intermediate the input and output devices for controlling the conduction state of the output devices as a function of the input devices and the predetermined logic levels.

摘要翻译： 逻辑电路响应于输入的逻辑组合提供预定的逻辑输出。 电路包括用于接收逻辑输入并且能够响应于所述输入的逻辑电平而呈现导通状态的多个输入装置。 至少一个输出设备连接到两个或多个输入设备。 提供具有预定逻辑电平的装置连接在输入和输出装置的中间，用于根据输入装置和预定的逻辑电平来控制输出装置的导通状态。

公开(公告)号：US3947865A

公开(公告)日：1976-03-30

申请号：US512919

申请日：1974-10-07

申请人： Lewis K. Russell

发明人： Lewis K. Russell

IPC分类号： H01L27/02 ,  H01L27/082 ,  H03K19/013 ,  H03K19/082 ,  H03K19/091 ,  H03K3/26 ,  H03K19/22 ,  H03K19/34

CPC分类号： H01L27/0821 ,  H01L27/0237 ,  H03K19/013 ,  H03K19/082 ,  H03K19/091

摘要： A collector-up binary structure of the type having spaced semiconductor regions forming a plurality of active devices for interconnection as a binary circuit is disclosed. The structure includes a semiconductor body of one conductivity having a planar surface, and spaced first, second, third and fourth transistors formed in said body. Fifth, sixth, seventh and eighth transistors are included, said fifth and sixth transistors being formed in the base regions of said second transistor and said seventh and eighth transistors being formed in the base region of said fourth transistor. Lead means provides ohmic contact to each of the respective regions of the respective transistors and interconnecting means is provided for connecting the plurality of active devices as a binary circuit. A structure further including ninth and tenth source transistors is also disclosed.

摘要翻译： 公开了一种具有间隔半导体区域的类型的集电极二进制结构，其形成用于互连的多个有源器件作为二进制电路。 该结构包括具有平坦表面的一种导电性的半导体本体，以及形成在所述主体中的间隔开的第一，第二，第三和第四晶体管。 包括第五，第六，第七和第八晶体管，所述第五和第六晶体管形成在所述第二晶体管的基极区域中，并且所述第七和第八晶体管形成在所述第四晶体管的基极区域中。 引线装置为相应晶体管的每个相应区域提供欧姆接触，并且提供互连装置用于将多个有源器件作为二进制电路连接。 还公开了还包括第九和第十源极晶体管的结构。

公开(公告)号：US3600642A

公开(公告)日：1971-08-17

申请号：US3600642D

申请日：1968-11-15

申请人： DAVID F ALLISON ,  LEWIS K RUSSELL

发明人： ALLISON DAVID F ,  RUSSELL LEWIS K

IPC分类号： H01L29/78 ,  H01L11/00 ,  H01C7/14

CPC分类号： H01L29/7816 ,  H01L29/0692 ,  H01L29/66681 ,  Y10S148/053 ,  Y10S148/085 ,  Y10S148/145 ,  Y10S148/167

摘要： MOS structure with precisely controlled channel length and method for making the same by utilization of the same mask for making the channel.

公开(公告)号：US4160988A

公开(公告)日：1979-07-10

申请号：US809615

申请日：1977-06-24

申请人： Lewis K. Russell

发明人： Lewis K. Russell

IPC分类号： H01L21/33 ,  H01L21/331 ,  H01L21/74 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/082 ,  H01L29/70 ,  H01L29/73 ,  H03K19/091 ,  H01L27/04

CPC分类号： H01L27/0828 ,  H01L21/74 ,  H01L21/8226 ,  H01L27/0237 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/087

摘要： A semiconductor structure, and method for fabrication, including a semiconductor body of one conductivity type having a major surface. A layer of opposite conductivity material is formed on said surface, said layer having an upper planar surface generally parallel to said major surface. Spaced first and second collector regions are carried by said layer. A third one conductivity region is formed in said layer spaced from said first and second region and extending to an exposed surface of said layer. A fourth region of opposite conductivity type is formed within said third region and extends to an exposed surface of said layer. The layer, third and forth regions form the respective regions of an opposite conductivity--one conductivity--opposite conductivity type source transistor. Additionally, the body, the layer and the first and second regions form the respective regions of a one conductivity--opposite conductivity--one conductivity switching transistor wherein said first and second regions form multiple collectors.

摘要翻译： 一种半导体结构及其制造方法，包括具有主表面的一种导电类型的半导体本体。 在所述表面上形成相反导电材料层，所述层具有大致平行于所述主表面的上平面。 间隔的第一和第二集电极区域由所述层承载。 在与所述第一和第二区域间隔开的所述层中形成第三个导电区域并延伸到所述层的暴露表面。 在所述第三区域内形成相反导电类型的第四区域并延伸到所述层的暴露表面。 层，第三和第四区域形成相反导电性的导电型导电型源极晶体管的相应区域。 此外，主体，层和第一和第二区域形成一个导电相反的导电一导电开关晶体管的相应区域，其中所述第一和第二区域形成多个集电极。

公开(公告)号：US3953866A

公开(公告)日：1976-04-27

申请号：US468938

申请日：1974-05-10

申请人： Lewis K. Russell

发明人： Lewis K. Russell

IPC分类号： G11C11/39 ,  G11C11/411 ,  H01L21/8229 ,  H01L27/07 ,  H01L27/082 ,  H01L27/102 ,  H03K3/289 ,  H01L27/02 ,  H01L27/04 ,  H03K3/26 ,  H03K5/00

CPC分类号： H03K3/289 ,  G11C11/39 ,  G11C11/4113 ,  H01L21/8229 ,  H01L27/0766 ,  H01L27/0828 ,  H01L27/1025 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/122 ,  Y10S148/139

摘要： A semiconductor memory cell, and a method for fabrication, including a one conductivity semiconductor body having a major surface and an opposite conductivity layer formed on said major surface said layer having a planar surface. Means extend from said planar surface through said layer to contact said body for isolating portions of said layer into first and second device regions. First and second device regions each include a one conductivity region formed in said device region extending to said planar surface, an opposite conductivity region formed within said one conductivity regions extending to said surface, and a metal-to-semiconductor contact carried by said device region at said planar surface. Lead means include means for ohmic interconnection of opposite conductivity regions formed in said first and second device regions, means for interconnecting said first device region and said one conductivity region formed in said second device region. Lead means further includes means for interconnection of said second device region and said one conductivity region formed in said first device region. Additional lead means is provided for coupling said metal-to-semiconductor contacts, said semiconductor body and said interconnected opposite conductivity regions with external circuitry.

摘要翻译： 一种半导体存储单元及其制造方法，包括一个具有主表面和相反导电层的导电半导体本体，所述主导表面和相对的导电层形成在所述主表面上，所述层具有平坦表面。 装置从所述平面延伸穿过所述层以接触所述主体，用于将所述层的部分隔离成第一和第二装置区域。 第一和第二器件区域各自包括形成在延伸到所述平坦表面的所述器件区域中的一个导电区域，形成在延伸到所述表面的所述一个导电区域内的相反导电区域以及由所述器件区域承载的金属与半导体接触 在所述平面上。 引线装置包括用于在所述第一和第二器件区域中形成的相反导电区域的欧姆互连的装置，用于互连所述第一器件区域和形成在所述第二器件区域中的所述一个导电区域的装置。 引线装置还包括用于互连所述第二器件区域和形成在所述第一器件区域中的所述一个导电区域的装置。 提供附加的引线装置，用于将所述金属 - 半导体触点，所述半导体主体和所述互连的相对导电区域与外部电路耦合。

公开(公告)号：US4097888A

公开(公告)日：1978-06-27

申请号：US766483

申请日：1977-02-07

申请人： Lewis K. Russell

发明人： Lewis K. Russell

IPC分类号： H01L27/02 ,  H01L29/72

CPC分类号： H01L27/0237

摘要： A high density semiconductor structure and method is disclosed including a semiconductor body of one conductivity having a substantially planar surface. A first region of one conductivity is formed in the body and extends to the surface. A layer of opposite conductivity is interposed between the first region and the body said layer having relatively thin and uniform walls which extend to separate the first region from the body. At least one opposite conductivity region is formed entirely within the first region and extends to the surface. An opposite conductivity region is formed in the body and overlaps a portion of the layer. Lead means are provided for contacting each of the respctive regions and the body. The collector-up injection logic structure thus formed requires little or no surface area for the injection source transistor.

摘要翻译： 公开了一种高密度半导体结构和方法，其包括具有基本平坦表面的一种导电性的半导体本体。 一个导电性的第一区域形成在主体中并延伸到表面。 在第一区域和主体之间插入相反电导率层，所述层具有相对较薄且均匀的壁，其延伸以将第一区域与主体分开。 至少一个相反的导电区域完全形成在第一区域内并延伸到表面。 在主体中形成相反的导电区域，并与层的一部分重叠。 提供引导装置用于接触每个呼吸区域和身体。 这样形成的集电极注入逻辑结构对于注入源晶体管来说几乎不需要或没有表面积。

公开(公告)号：US3970865A

公开(公告)日：1976-07-20

申请号：US522433

申请日：1974-11-11

申请人： Lewis K. Russell

发明人： Lewis K. Russell

IPC分类号： G11C8/10 ,  H03K19/0944 ,  H03M7/00 ,  H03K19/08

CPC分类号： H03K19/09441 ,  G11C8/10 ,  H03M7/00

摘要： A decode driver useful in decoders for memory circuits. A plurality of transistors are connected in series between a first reference potential terminal and an output terminal. A second plurality of transistors are connected in parallel between a second reference potential terminal and the output terminal. Each of the transistors receives an input which functions to turn the transistors either on or off. The coding of the inputs determines whether the transistors to which the respective inputs are connected are turned on or off which in turn controls whether or not the output terminal is coupled to the first reference potential terminal or the second reference potential terminal.

摘要翻译： 用于存储器电路的解码器的解码驱动器。 多个晶体管串联连接在第一参考电位端子和输出端子之间。 第二多个晶体管并联连接在第二参考电位端子和输出端子之间。 每个晶体管接收用于使晶体管导通或断开的功能的输入。 输入的编码确定连接各个输入端的晶体管是否导通或关断，这又控制输出端是否耦合到第一参考电位端或第二参考电位端。

公开(公告)号：US4233674A

公开(公告)日：1980-11-11

申请号：US931591

申请日：1978-08-07

申请人： Lewis K. Russell ,  David Kleitman

发明人： Lewis K. Russell ,  David Kleitman

IPC分类号： G11C11/417 ,  G11C11/418 ,  G11C29/00 ,  H01L27/118 ,  G11C11/40

CPC分类号： G11C29/78 ,  G11C11/417 ,  G11C11/418 ,  H01L27/11803

摘要： In a method of configuring an integrated circuit provided in a semiconductor body having a surface and spaced semiconductor circuits formed in the body, intercoupling means are formed in the body adjacent each of said circuits, and connected to said circuits. A plurality of conductive paths are formed between said intercoupling means and carried by the body. Each intercoupling means includes a plurality of semiconductor regions formed in the semiconductor body, said regions in combination capable of assuming a first low impedance condition and a second high impedance condition to thereby selectively couple each of said circuits to selected conductive paths or decouple each of said circuits from said conductive paths. In a specific embodiment of the invention a massive monolithic integrated circuit is configured using intercoupling means in combination with small scale random access memory semiconductor circuits. A static MOS random access memory having a 2,048 word capacity, with 9 bits/word and an 11 bit address is provided.

摘要翻译： 在配置在半导体本体中的集成电路的方法中，该半导体本体具有形成在主体中的表面和间隔开的半导体电路，相互耦合装置形成在与每个所述电路相邻的主体中并连接到所述电路。 在所述相互联接装置之间形成多个导电路径并由主体承载。 每个相互耦合装置包括形成在半导体本体中的多个半导体区域，所述区域组合能够呈现第一低阻抗条件和第二高阻抗条件，从而选择性地将每个所述电路耦合到选定的导电路径或者将每个所述 电路从所述导电路径。 在本发明的一个具体实施例中，使用与小规模随机存取存储器半导体电路组合的相互耦合装置来配置大块单片集成电路。 提供具有2048字容量的静态MOS随机存取存储器，其具有9位/字和11位地址。

公开(公告)号：USRE29962E

公开(公告)日：1979-04-10

申请号：US891164

申请日：1978-03-28

申请人： Lewis K. Russell

发明人： Lewis K. Russell

IPC分类号： H01L27/02 ,  H01L27/082 ,  H03K19/013 ,  H03K19/082 ,  H03K19/091

CPC分类号： H01L27/0821 ,  H01L27/0237 ,  H03K19/013 ,  H03K19/082 ,  H03K19/091

摘要： A collector-up binary structure of the type having spaced semiconductor regions forming a plurality of active devices for interconnection as a binary circuit is disclosed. The structure includes a semiconductor body of one conductivity having a planar surface, and spaced first, second, third and fourth transistors formed in said body. Fifth, sixth, seventh and eighth transistors are included, said fifth and sixth transistors being formed in the base regions of said second transistor and said seventh and eighth transistors being formed in the base region of said fourth transistor. Lead means provides ohmic contact to each of the respective regions of the respective transistors and interconnecting means is provided for connecting the plurality of active devices as a binary circuit. A structure further including ninth and tenth source transistors is also disclosed.