公开(公告)号：US4233674A

公开(公告)日：1980-11-11

申请号：US931591

申请日：1978-08-07

申请人： Lewis K. Russell ,  David Kleitman

发明人： Lewis K. Russell ,  David Kleitman

IPC分类号： G11C11/417 ,  G11C11/418 ,  G11C29/00 ,  H01L27/118 ,  G11C11/40

CPC分类号： G11C29/78 ,  G11C11/417 ,  G11C11/418 ,  H01L27/11803

摘要： In a method of configuring an integrated circuit provided in a semiconductor body having a surface and spaced semiconductor circuits formed in the body, intercoupling means are formed in the body adjacent each of said circuits, and connected to said circuits. A plurality of conductive paths are formed between said intercoupling means and carried by the body. Each intercoupling means includes a plurality of semiconductor regions formed in the semiconductor body, said regions in combination capable of assuming a first low impedance condition and a second high impedance condition to thereby selectively couple each of said circuits to selected conductive paths or decouple each of said circuits from said conductive paths. In a specific embodiment of the invention a massive monolithic integrated circuit is configured using intercoupling means in combination with small scale random access memory semiconductor circuits. A static MOS random access memory having a 2,048 word capacity, with 9 bits/word and an 11 bit address is provided.

摘要翻译： 在配置在半导体本体中的集成电路的方法中，该半导体本体具有形成在主体中的表面和间隔开的半导体电路，相互耦合装置形成在与每个所述电路相邻的主体中并连接到所述电路。 在所述相互联接装置之间形成多个导电路径并由主体承载。 每个相互耦合装置包括形成在半导体本体中的多个半导体区域，所述区域组合能够呈现第一低阻抗条件和第二高阻抗条件，从而选择性地将每个所述电路耦合到选定的导电路径或者将每个所述 电路从所述导电路径。 在本发明的一个具体实施例中，使用与小规模随机存取存储器半导体电路组合的相互耦合装置来配置大块单片集成电路。 提供具有2048字容量的静态MOS随机存取存储器，其具有9位/字和11位地址。

公开(公告)号：US4122540A

公开(公告)日：1978-10-24

申请号：US675776

申请日：1976-04-12

申请人： Lewis K. Russell ,  David Kleitman

发明人： Lewis K. Russell ,  David Kleitman

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C29/00 ,  H01L23/52 ,  H01L23/525 ,  H01L23/66 ,  H01L27/118 ,  G11C11/40

CPC分类号： H01L27/11803 ,  G11C16/0408 ,  G11C29/785 ,  H01L23/52 ,  H01L23/5256 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/3011

摘要： In an integrated circuit, a semiconductor body having a surface, spaced semiconductor circuits formed in the body, intercoupling means formed in the body adjacent each of said circuits, and connected to said circuits. A plurality of conductive paths are formed between said intercoupling means and carried by the body. Each intercoupling means includes a plurality of semiconductor regions formed in the semiconductor body, said regions in combination capable of assuming a first low impedance condition and a second high impedance condition to thereby selectively couple each of said circuits to selected conductive paths or decouple each of said circuits from said conductive paths. In a specific embodiment of the invention a massive monolithic integrated circuit is configured using intercoupling means in combination with small scale random access memory semiconductor circuits. A static MOS random access memory having a 2,048 word capacity, with 9 bits/word and an 11 bit address is provided.

摘要翻译： 在集成电路中，具有形成在主体中的间隔开的半导体电路的表面的半导体主体，与所述电路中的每一个相邻地形成在所述主体中并连接到所述电路的互耦装置。 在所述相互联接装置之间形成多个导电路径并由主体承载。 每个相互耦合装置包括形成在半导体本体中的多个半导体区域，所述区域组合能够采取第一低阻抗条件和第二高阻抗条件，从而选择性地将每个所述电路耦合到选定的导电路径，或者将每个所述 电路从所述导电路径。 在本发明的一个具体实施例中，使用与小规模随机存取存储器半导体电路组合的相互耦合装置来配置大块单片集成电路。 提供具有2048字容量的静态MOS随机存取存储器，其具有9位/字和11位地址。