公开(公告)号：US5930638A

公开(公告)日：1999-07-27

申请号：US914474

申请日：1997-08-19

Applicant: Ronald E. Reedy ,  Mark L. Burgener

Inventor： Ronald E. Reedy ,  Mark L. Burgener

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/86 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786 ,  H01L29/8605

CPC classification number: H01L21/0242 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/86 ,  H01L27/1112 ,  H01L27/12 ,  H01L27/1203 ,  H01L28/20 ,  H01L29/78621 ,  H01L29/78654 ,  H01L29/78657 ,  H01L29/8605 ,  Y10S148/136

Abstract: A diffused resistor and a method for making the diffused resistor are disclosed. The diffused resistor is formed in a substantially pure portion of the thin semiconductor layer that is formed on an insulating substrate. The thin semiconductor layer has low a number of defects and mid-band gap states. This portion may be located in an electrically isolated region of the thin semiconductor layer. A resistive region is used to provide the resistance of the diff-used resistor. Contact regions are provided continguous with the the resistive region. The diff-used resistor can be formed by themselves or in conjunction with other circuit elements, such as a MOSFET, for example. Accordingly, also disclosed is a method for making the diffused resitor in conjunction with a MOSFET. The diffused resistor and the MOSFET are formed in electrically isolated semiconductor islands. The electrically isolated semiconductor islands are formed from the high quality thin semiconductor layer. Both non-silicide and silicide processes are disclosed. Also disclosed is a differential amplifier circuit that uses the disclosed diffused resistor embodiments.

Abstract translation: 公开了扩散电阻器和制造扩散电阻器的方法。 扩散电阻器形成在形成在绝缘基板上的薄半导体层的基本纯净部分中。 薄半导体层具有少量缺陷和中带隙状态。 该部分可以位于薄半导体层的电隔离区域中。 电阻区域用于提供差分电阻器的电阻。 接触区域与电阻区域相连。 差分电阻器可以由其本身或与例如MOSFET等其它电路元件组合形成。 因此，还公开了一种使扩散电阻器与MOSFET结合的方法。 扩散电阻器和MOSFET形成在电隔离的半导体岛中。 电绝缘半导体岛由高质量的薄半导体层形成。 公开了非硅化物和硅化物工艺。 还公开了使用所公开的扩散电阻器实施例的差分放大器电路。

公开(公告)号：US5880001A

公开(公告)日：1999-03-09

申请号：US956829

申请日：1997-10-23

Applicant: Hans R. Camenzind

Inventor： Hans R. Camenzind

IPC: H01L21/329 ,  H01L29/8605 ,  H01L21/8222

CPC classification number: H01L29/66166 ,  H01L29/8605 ,  Y10S148/136

Abstract: An epitaxial pinched resistor includes a semiconductor substrate of a first conductivity type having a surface on which an epitaxial layer of a second conductivity type grown. An up isolation region of the first conductivity type is diffused from the surface of the semiconductor substrate up into the epitaxial layer. A first down isolation region of the first conductivity type is diffused down into the epitaxial layer and overlapping with the up isolation region. The first down isolation region and the up isolation region isolate a portion of the epitaxial layer to be used to conduct a current. A second down isolation region of the first conductivity type is diffused down into the epitaxial layer between first and second contact surface areas of the epitaxial layer and into the portion of the epitaxial layer used to conduct the current. The second down isolation region is diffused a depth approximately equal to the first down isolation region so as to reduce a conductive cross-sectional area of the epitaxial layer. First and second ohmic contacts of the second conductivity type are diffused into the first and second contact surface areas of the epitaxial layer. The present invention also provides a method of forming an epitaxial pinched resistor.

Abstract translation: 外延夹持电阻器包括具有第一导电类型的半导体衬底，其具有生长第二导电类型的外延层的表面。 第一导电类型的向上隔离区域从半导体衬底的表面扩散到外延层中。 第一导电类型的第一下降隔离区向下扩散到外延层中并与上隔离区重叠。 第一下降隔离区域和向上隔离区域隔离用于导通电流的外延层的一部分。 第一导电类型的第二下降隔离区域向下扩散到外延层的第一和第二接触表面区域之间的外延层中，并扩散到用于导通电流的外延层的部分中。 第二下降隔离区域扩散大约等于第一下降隔离区域的深度，以便减小外延层的导电横截面面积。 第二导电类型的第一和第二欧姆接触扩散到外延层的第一和第二接触表面区域中。 本发明还提供一种形成外延夹持电阻器的方法。

公开(公告)号：US5691214A

公开(公告)日：1997-11-25

申请号：US725760

申请日：1996-10-04

Applicant: Masaru Wakabayashi

Inventor： Masaru Wakabayashi

IPC: H01L21/265 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/73 ,  H01L29/732

CPC classification number: H01L21/8222 ,  H01L27/0658 ,  Y10S148/136 ,  Y10S148/163

Abstract: A method of manufacturing a semiconductor device furnished on a silicon substrate with a bipolar element part and a resistance element part formed of an impurity diffusion layer, having (a) a step of forming a first oxide film on said silicon substrate and on the component elements formed on said substrate throughout the entire surface thereof, (b) a step of selectively and sequentially removing the part of said first oxide film corresponding to the base region of said bipolar element part and the surface of said silicon substrate directly underlying said first oxide film and, at the same time, cleaning the freshly exposed surface, (c) a step of forming a second oxide film on said silicon substrate and said component elements formed thereon throughout the entire surface thereof thereby differentiating the thickness of the oxide film formed on said base region and the thickness of the oxide film formed on said resistance element part, and (d) a step of selectively and instantaneously implanting an ion into said bipolar element part and said resistance element part.

Abstract translation: 一种制造半导体器件的方法，所述半导体器件具有双极元件部分和由杂质扩散层形成的电阻元件部分的硅衬底，所述半导体器件具有（a）在所述硅衬底上形成第一氧化物膜的步骤和所述元件元件 在其整个表面上形成在所述基板上，（b）选择性地并且顺序地去除与所述双极元件部分的基极区域相对应的所述第一氧化物膜的部分以及直接位于所述第一氧化物膜下方的所述硅衬底的表面的步骤 并且同时清洁新曝光的表面，（c）在所述硅衬底上形成第二氧化物膜的步骤和在其整个表面上形成的所述元件，从而使形成在所述硅衬底上的氧化膜的厚度区分所形成的氧化膜的厚度 基底区域和形成在所述电阻元件部分上的氧化膜的厚度，以及（d）选择性地和即时地形成的步骤 将离子种植到所述双极元件部分和所述电阻元件部分中。

公开(公告)号：US5679593A

公开(公告)日：1997-10-21

申请号：US595232

申请日：1996-02-01

Applicant: James E. Miller, Jr. ,  Manny K. F. Ma

Inventor： James E. Miller, Jr. ,  Manny K. F. Ma

IPC: H01L21/329 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/8605 ,  H01L21/265

CPC classification number: H01L29/66166 ,  H01L21/8238 ,  H01L27/0629 ,  H01L29/8605 ,  Y10S148/136

Abstract: The present invention teaches fabrication of a high-resistance integrated circuit diffusion resistor that uses standard CMOS process steps. By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created during NMOS source/drain implant may be counterdoped during PMOS source/drain implants and vice-versa. By appropriate choice of relative concentrations of a resistor dopant and counterdopant, and choice of diffusion depths, junction diodes can be formed which create a pinched resistor by constricting the current flow. The relative dopant concentrations can also be chosen to create regions of light effective doping within the diffusion resistor rather than creating junction diodes.

Abstract translation: 本发明教导了制造使用标准CMOS工艺步骤的高电阻集成电路扩散电阻器。 在源极/漏极扩散区的离子注入期间通过适当的掩蔽，在NMOS源极/漏极注入期间产生的扩散电阻器可能在PMOS源极/漏极注入期间被反掺杂，反之亦然。 通过适当选择电阻器掺杂剂和反掺杂剂的相对浓度以及扩散深度的选择，可以形成结二极管，其通过限制电流流动而产生夹持电阻。 还可以选择相对掺杂剂浓度以在扩散电阻器内产生光有效掺杂的区域，而不是产生结二极管。

公开(公告)号：US5672551A

公开(公告)日：1997-09-30

申请号：US462176

申请日：1995-06-05

Applicant: Clifford D. Fung

Inventor： Clifford D. Fung

IPC: G01L9/00 ,  H01L21/77

CPC classification number: G01L9/0055 ,  G01L9/0042 ,  Y10S148/136 ,  Y10S438/97

Abstract: A semiconductor pressure sensor utilizes single-crystal silicon piezoresistive gage elements dielectrically isolated by silicon oxide from other such elements, and utilizes an etched silicon substrate with an etch stop. P-type implants form p-type piezoresistive gage elements and form p+ interconnections to connect the sensor to external electrical devices. The diaphragm is made from epitaxially-grown single-crystal silicon. Passivation nitride can be used for additional dielectric isolation. One practice of the invention provides over-range cavity protection, and thus increased robustness, by forming an over-range stop for the diaphragm through localized oxygen ion implantation and etching.

Abstract translation: 半导体压力传感器利用由其他这样的元件通过氧化硅介电隔离的单晶硅压阻元件，并且利用具有蚀刻停止层的蚀刻硅衬底。 P型植入物形成p型压阻测量元件并形成p +互连以将传感器连接到外部电气设备。 隔膜由外延生长的单晶硅制成。 钝化氮化物可用于额外的电介质隔离。 本发明的一个实践通过通过局部氧离子注入和蚀刻形成用于隔膜的超量程停止来提供超范围腔保护，从而提高鲁棒性。

公开(公告)号：US5652181A

公开(公告)日：1997-07-29

申请号：US585084

申请日：1996-01-16

Applicant: Randhir P. S. Thakur

Inventor： Randhir P. S. Thakur

IPC: H01L21/02 ,  H01L21/293 ,  H01L21/321

CPC classification number: H01L28/24 ,  Y10S148/136

Abstract: The present invention develops several methods used in a semiconductor fabrication process to form a resistive material having a specific resistive value. A first method uses the steps of: forming a titanium layer over a silicon substrate; and subjecting the titanium layer to a rapid thermal processing cycle. A second method uses the steps of: forming a titanium layer over a silicon substrate; subjecting the titanium layer to a rapid thermal processing cycle; and forming a titanium nitride layer over the thermally processed titanium. A third method uses the steps of: forming an insulating layer over a silicon substrate; forming an undoped polysilicon layer over the insulating layer; forming a titanium layer over the polysilicon layer; subjecting the titanium layer to a rapid thermal processing cycle; and forming a titanium nitride layer over the thermally processed titanium. Additionally, the resistive structure can be capped using a nitride layer.

Abstract translation: 本发明开发了在半导体制造工艺中使用的几种方法来形成具有特定电阻值的电阻材料。 第一种方法使用以下步骤：在硅衬底上形成钛层; 并使钛层经受快速热处理循环。 第二种方法使用以下步骤：在硅衬底上形成钛层; 使钛层经受快速热处理循环; 并在热处理的钛上形成氮化钛层。 第三种方法使用以下步骤：在硅衬底上形成绝缘层; 在所述绝缘层上形成未掺杂的多晶硅层; 在所述多晶硅层上形成钛层; 使钛层经受快速热处理循环; 并在热处理的钛上形成氮化钛层。 此外，电阻结构可以使用氮化物层进行封盖。

公开(公告)号：US5594269A

公开(公告)日：1997-01-14

申请号：US322387

申请日：1994-10-12

Applicant: Charles R. Spinner, III ,  Fu-Tai Liou

Inventor： Charles R. Spinner, III ,  Fu-Tai Liou

IPC: H01L21/02 ,  H01L27/11 ,  H01L21/768 ,  H01L23/52

CPC classification number: H01L28/20 ,  H01L27/1112 ,  Y10S148/136 ,  Y10S257/904

Abstract: An integrated circuit structure contains both highly resistive regions and highly conductive interconnect regions in a single layer of polycrystalline silicon. The resistive regions have a smaller cross section than the interconnect regions as a result of partial oxidation. Their thickness and width are reduced from that of the interconnect regions. The partial oxidation leaves an oxide region, derived from polycrystalline silicon, on both the top and sides of the resistive regions.

Abstract translation: 集成电路结构在单层多晶硅中包含高电阻区域和高导电互连区域。 由于部分氧化，电阻区域具有比互连区域更小的横截面。 它们的厚度和宽度比互连区域的厚度和宽度减小。 部分氧化在电阻区域的顶部和侧面留下来自多晶硅的氧化物区域。

公开(公告)号：US5547896A

公开(公告)日：1996-08-20

申请号：US387233

申请日：1995-02-13

Applicant: Jack H. Linn ,  John T. Gasner ,  Stephen J. Gaul ,  Chris A. McCarty

Inventor： Jack H. Linn ,  John T. Gasner ,  Stephen J. Gaul ,  Chris A. McCarty

IPC: H05K3/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H01L21/70

CPC classification number: H01L28/24 ,  H01L21/32134 ,  H01L21/32139 ,  Y10S148/136

Abstract: In a method of etching a thin film resistor material, such as NiCr or CrSi, and of producing a thin film resistor, a non-photoresist hard mask is deposited on an exposed surface of thin film resistor material, a delineated portion of the hard mask is etched with a hydrogen peroxide etchant that does not affect the thin film resistor material to expose the material therebeneath, and the exposed thin film resistor material is etched with a second etchant that does not affect the hard mask. The second etchant may be sulfuric acid heated to greater than 125.degree. C. for NiCr or a mixture of phosphoric acid, nitric acid and hydrofluoric acid for CrSi. The hard mask preferably comprises TiW.

Abstract translation: 在蚀刻诸如NiCr或CrSi的薄膜电阻器材料和制造薄膜电阻器的方法中，将非光致抗蚀剂硬掩模沉积在薄膜电阻器材料的暴露表面上，硬掩模的描绘部分 用不影响薄膜电阻器材料以暴露其下的材料的过氧化氢蚀刻剂进行蚀刻，并且用不影响硬掩模的第二蚀刻剂蚀刻暴露的薄膜电阻器材料。 第二蚀刻剂可以是NiCr或硫酸用于CrSi的磷酸，硝酸和氢氟酸的混合物加热到大于125℃的硫酸。 硬掩模优选包含TiW。

公开(公告)号：US5514617A

公开(公告)日：1996-05-07

申请号：US266504

申请日：1994-06-27

Applicant: Chwen-Ming Liu

Inventor： Chwen-Ming Liu

IPC: H01L21/02 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/70 ,  H01L27/00

CPC classification number: H01L28/20 ,  H01L27/11 ,  H01L27/1112 ,  Y10S148/136 ,  Y10S257/904

Abstract: A device and a method of manufacture of a semiconductor device on a semiconductor substrate including an SRAM cell with a resistor comprises forming a first polycrystalline silicon containing layer on the semiconductor substrate, patterning and etching the first polycrystalline silicon containing layer to form steps on either side thereof, forming a dielectric layer over the first polycrystalline silicon containing layer with the steps on either side of the first polycrystalline silicon containing layer, forming a blanket of a second polycrystalline silicon containing layer extending over the interpolysilicon layer, and ion implanting the second polycrystalline silicon containing layer in a blanket implant of a light dose of dopant including ion implanting resistive regions with far higher resistivity in the regions over the steps.

Abstract translation: 在包括具有电阻器的SRAM单元的半导体衬底上制造半导体器件的器件和方法包括在半导体衬底上形成第一多晶硅层，对第一多晶硅含量层进行图案化和蚀刻以在两侧形成步骤 在所述第一多晶硅含硅层上形成电介质层，所述第一多晶硅含有层的任一侧上具有台阶，形成在所述多晶硅层上延伸的第二多晶硅含量层的覆盖层，以及离子注入所述第二多晶硅 包含光剂量的掺杂剂的包覆层植入物，其包括在步骤上的区域中具有远高于电阻率的离子注入电阻区域。

公开(公告)号：US5496762A

公开(公告)日：1996-03-05

申请号：US253049

申请日：1994-06-02

Applicant: Gurtej S. Sandhu ,  Trung T. Doan ,  David A. Cathey

Inventor： Gurtej S. Sandhu ,  Trung T. Doan ,  David A. Cathey

IPC: H01L21/02 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/70

CPC classification number: H01L28/24 ,  H01L27/11 ,  H01L27/1112 ,  Y10S148/117 ,  Y10S148/136

Abstract: This invention is a process for making resistor structures having high stability and reliability characteristics. Process parameters are easily modifiable to adjust the resistivity of the structures. A layer of titanium nitride, which may contain certain impurities such as carbon, is deposited via chemical vapor deposition by pyrolization of an organometallic precursor compound of the formula Ti(NR.sub.2).sub.4 either alone or in the presence of either a nitrogen source (e.g. ammonia or nitrogen gas) or an activated species (which may include a halogen, NH.sub.3, or hydrogen radicals, or combinations thereof). The TiN film is then oxidized to create a structure that demonstrates highly stable, highly reliable resistive characteristics, with bulk resistivity values in giga ohm range. In a preferred embodiment of the invention, a predominantly amorphous titanium carbonitride film is deposited on an insulative substrate in a chemical vapor deposition chamber. A layer of titanium is then deposited on top of the titanium carbonitride film. The titanium layer is then patterned with photoresist. The exposed titanium is then etched with a reagent that is selective for titanium over titanium carbonitride (HF, for example, has better than 10:1 selectivity) so that the etch essentially stops when the titanium carbonitride film is exposed. The exposed titanium carbonitride film is then oxidized to achieve the desired resistivity.

Abstract translation: 本发明是制造具有高稳定性和可靠性特性的电阻器结构的方法。 工艺参数易于修改以调整结构的电阻率。 可以通过化学气相沉积通过单独或在氮源（例如氨）的存在下热分解式Ti（NR 2）4的有机金属前体化合物来沉积可能含有某些杂质如碳的氮化钛层 或氮气）或活化物质（其可以包括卤素，NH 3或氢基团，或其组合）。 然后将TiN膜氧化，形成表现出高度稳定，高度可靠的电阻特性的结构，体电阻率为千兆欧姆范围。 在本发明的优选实施方案中，主要是无定形的碳氮化钛膜沉积在化学气相沉积室中的绝缘衬底上。 然后将钛层沉积在碳氮化钛膜的顶部。 然后用光致抗蚀剂对钛层进行图案化。 然后用暴露的钛蚀刻钛对碳氮化钛（HF，例如优于10：1选择性）选择性的试剂，使得当碳氮化钛膜暴露时，蚀刻基本上停止。 然后将暴露的碳氮化钛膜氧化以获得所需的电阻率。