公开(公告)号：US6124153A

公开(公告)日：2000-09-26

申请号：US680062

申请日：1996-07-15

Applicant: Joo-hyung Lee ,  Yong-suk Jin

Inventor： Joo-hyung Lee ,  Yong-suk Jin

IPC: G02F1/136 ,  G02F1/1368 ,  H01L21/316 ,  H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L21/84

CPC classification number: H01L29/42364 ,  H01L29/42384 ,  H01L29/66757 ,  Y10S148/043 ,  Y10S148/163 ,  Y10S438/981

Abstract: A method for manufacturing a polysilicon thin film transistor (TFT) according to the present invention reduces the electric field near the drain junction by varying partially the thickness of a gate insulating layer through a post oxide process. A polysilicon layer is patterned to become an active layer and a chemical vapor deposition oxide film deposited. By thermal oxidation a thermal oxide film is formed under the chemical vapor deposition oxide film. A gate electrode made of polysilicon is formed on the gate insulating layer. Thermal oxidation is performed to make the end portions of the thermal oxide film thicker than the portion under the gate electrode of the thermal oxide film. With this process, the electric field near the drain junction region is reduced and thus the leakage currents of the TFT decrease. In addition, the method in this invention is very simple compared with the conventional methods of obtaining a LDD structure and on-current is not reduced.

Abstract translation: 根据本发明的制造多晶硅薄膜晶体管（TFT）的方法通过后氧化处理部分地改变栅极绝缘层的厚度来减小漏极结附近的电场。 图案化多晶硅层成为有源层和沉积化学气相沉积氧化膜。 通过热氧化，在化学气相沉积氧化膜下形成热氧化膜。 在栅极绝缘层上形成由多晶硅制成的栅电极。 进行热氧化以使热氧化膜的端部比热氧化膜的栅电极下方的部分厚。 通过该处理，漏极结区域附近的电场减小，因此TFT的漏电流下降。 此外，本发明的方法与获得LDD结构的常规方法相比非常简单，并且导通电流不降低。

公开(公告)号：US5716863A

公开(公告)日：1998-02-10

申请号：US655471

申请日：1996-05-30

Applicant: Norihisa Arai

Inventor： Norihisa Arai

IPC: H01L27/04 ,  H01L21/28 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/06 ,  H01L27/088 ,  H01L27/10 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L27/11526 ,  H01L21/28061 ,  H01L21/823462 ,  H01L27/1052 ,  H01L27/11541 ,  Y10S148/163 ,  Y10S438/981

Abstract: A plurality of device isolation insulating layers are formed on the surface of a semiconductor substrate. A gate insulating layer is formed on the substrate surface between each device isolation insulating layer. After that, a first polysilicon layer is deposited over the entire surface of the substrate. The first polysilicon layer is patterned so that it is left on a region where a first transistor is to be formed and a resistive element is defined on one of the device isolation insulating layers. A silicon oxide layer is formed on a portion of the first polysilicon layer that is left to define the resistive element. This silicon oxide layer prevents impurities from penetrating into the polysilicon defining the resistive element and acts as an etching stopper for the polysilicon when a second polysilicon layer and a layer of refractory metal is removed.

Abstract translation: 在半导体衬底的表面上形成多个器件隔离绝缘层。 在每个器件隔离绝缘层之间的衬底表面上形成栅极绝缘层。 之后，在衬底的整个表面上沉积第一多晶硅层。 图案化第一多晶硅层，使其保留在要形成第一晶体管的区域上，并且在器件隔离绝缘层中的一个上限定电阻元件。 在第一多晶硅层的形成电阻元件的部分上形成氧化硅层。 该氧化硅层防止杂质渗透到限定电阻元件的多晶硅中，并且当去除第二多晶硅层和难熔金属层时，其用作多晶硅的蚀刻阻挡层。

公开(公告)号：US5712203A

公开(公告)日：1998-01-27

申请号：US570340

申请日：1995-12-11

Applicant: Chen-Chung Hsu

Inventor： Chen-Chung Hsu

IPC: H01L21/8246

CPC classification number: H01L27/11246 ,  Y10S148/163 ,  Y10S438/981

Abstract: A process for fabricating memory cells of a read-only memory (ROM) device is disclosed. First, a silicon dioxide layer and a silicon nitride layer are successively formed on the surface of a silicon substrate. These layers are patterned by etching to form a plurality of parallel barrier strips extending along a first direction on the surface of the substrate. Impurities are then implanted into the silicon substrate by using the barrier strips as masks, to form a plurality of buried bit lines in the areas between the barrier strips. Next, insulating sidewall spacers are formed on the sidewalls of the barrier strips. A metal silicide layer is then formed over the exposed surface of the buried bit lines in a self-aligned process. A thick dielectric layer is then formed overlying the barrier strips, the insulating sidewall spacers, and the metal silicide layer. The upper portions of the thick dielectric layer, the insulating sidewall spacers, and the silicon nitride layer are then polished to form a planar surface. Thereafter, portions of the barrier strips that cover the designated coding regions of the memory cells are removed to expose the silicon substrate. A gate oxide layer is formed on the exposed surface of the silicon substrate. Finally, a conducting layer is formed overlying the entire substrate surface. The conducting layer is then patterned by etching to form a plurality of strip-shaped word lines of the memory cells extending along a second direction which is substantially orthogonal to the first direction.

Abstract translation: 公开了一种用于制造只读存储器（ROM）器件的存储器单元的工艺。 首先，在硅衬底的表面上依次形成二氧化硅层和氮化硅层。 通过蚀刻对这些层进行图案化，以形成沿衬底表面上的第一方向延伸的多个平行阻挡带。 然后通过使用阻挡条作为掩模将杂质注入到硅衬底中，以在阻挡条之间的区域中形成多个掩埋位线。 接下来，在隔离带的侧壁上形成绝缘侧壁间隔物。 然后在自对准工艺中在掩埋位线的暴露表面上形成金属硅化物层。 然后形成覆盖阻挡条，绝缘侧壁间隔物和金属硅化物层的厚介电层。 然后对厚电介质层，绝缘侧墙和氮化硅层的上部进行抛光以形成平面。 此后，去除覆盖存储器单元的指定编码区域的阻挡条的部分以露出硅衬底。 在硅衬底的暴露表面上形成栅氧化层。 最后，形成覆盖整个基板表面的导电层。 然后通过蚀刻对导电层进行构图，以形成沿着基本上与第一方向正交的第二方向延伸的多个存储单元的条形字线。

公开(公告)号：US5614425A

公开(公告)日：1997-03-25

申请号：US622270

申请日：1996-03-27

Applicant: Koji Kimura ,  Hiroshi Naruse

Inventor： Koji Kimura ,  Hiroshi Naruse

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/732 ,  H01L29/737 ,  H01L21/265

CPC classification number: H01L29/66287 ,  H01L29/732 ,  Y10S148/163

Abstract: An N type diffusion layer as a collector is formed on a P type silicon substrate, and a field oxide film is formed on this diffusion layer. An MoSi.sub.2 film is formed on this field oxide film and a first opening is formed on those field oxide film and MoSi.sub.2 film to expose the diffusion layer. An N type layer is selectively epitaxially grown only on the bottom of the first opening. A base layer is formed on the N type layer, the side wall of the first opening and the MoSi.sub.2 film. The base layer on the N type layer is formed by epitaxial growth, while the base layer on the side wall of the first opening and the MoSi.sub.2 film is formed in a polycrystalline state. A first silicon oxide film is formed on this based layer. The first silicon oxide film is thinner on the polycrystalline base layer than on the epitaxially grown base layer. The first silicon oxide film is subjected to anisotropic etching to expose only the surface of the epitaxially grown base layer. An N type silicon film as an emitter is selectively grown only on this exposed base layer.

Abstract translation: 在P型硅衬底上形成作为集电体的N型扩散层，在该扩散层上形成场氧化膜。 在该场氧化膜上形成MoSi 2膜，在该场氧化膜和MoSi 2膜上形成第一开口，使扩散层露出。 仅在第一开口的底部选择性地外延生长N型层。 在N型层，第一开口的侧壁和MoSi 2膜上形成基层。 通过外延生长形成N型层上的基底层，而第一开口的侧壁上的基底层和MoSi 2膜形成为多晶态。 在该基层上形成第一氧化硅膜。 第一氧化硅膜在多晶基底层上比在外延生长的基底层上薄。 对第一氧化硅膜进行各向异性蚀刻，仅露出外延生长的基底层的表面。 作为发射极的N型硅膜仅在该露出的基底层上选择性地生长。

公开(公告)号：US5330920A

公开(公告)日：1994-07-19

申请号：US77570

申请日：1993-06-15

Applicant: Hamid R. Soleimani ,  Brian S. Doyle ,  Ara Philipossian

Inventor： Hamid R. Soleimani ,  Brian S. Doyle ,  Ara Philipossian

IPC: H01L21/28 ,  H01L21/32 ,  H01L21/8234 ,  H01L29/51 ,  H01L21/265

CPC classification number: H01L21/28185 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/32 ,  H01L21/823462 ,  H01L29/518 ,  Y10S148/118 ,  Y10S148/163 ,  Y10S438/981

Abstract: A method of controlling gate oxide thickness in the fabrication of semiconductor devices wherein a sacrificial gate oxide layer is formed on a semiconductor substrate surface. Nitrogens ions are implanted into select locations of the substrate through the sacrificial gate oxide layer, and the substrate and the gate oxide layer are then thermally annealed. The sacrificial gate oxide layer is then removed and a gate oxide layer is then formed on the substrate layer wherein the portion of the gate oxide layer formed on the nitrogen ion implanted portion of the substrate is thinner than the portion of the gate oxide layer formed on the non-nitrogen ion implanted portion.

Abstract translation: 在半导体器件的制造中控制栅极氧化物厚度的方法，其中在半导体衬底表面上形成牺牲栅极氧化物层。 硝基离子通过牺牲栅极氧化物层注入到衬底的选择位置中，然后将衬底和栅极氧化物层热退火。 然后去除牺牲栅极氧化物层，然后在衬底层上形成栅极氧化物层，其中形成在衬底的氮离子注入部分上的栅极氧化物层的部分比形成在栅极氧化物层上的部分更薄 非氮离子注入部分。

公开(公告)号：US5106768A

公开(公告)日：1992-04-21

申请号：US575846

申请日：1990-08-31

Applicant: Kuo-Yun Kuo

Inventor： Kuo-Yun Kuo

IPC: H01L21/265 ,  H01L21/316 ,  H01L21/8238

CPC classification number: H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/2652 ,  H01L21/31662 ,  H01L21/823814 ,  Y10S148/082 ,  Y10S148/116 ,  Y10S148/163 ,  Y10S438/981

Abstract: The present method uses a one block out mask method for forming both the N channel and P channel MOS field effect transistors by providing a special oxidizing method that grows sufficient silicon oxide upon the already formed N+ source/drain regions which is sufficient to block the P+ ion implantation which forms the P channel device from the N channel device area.

Abstract translation: 本方法使用一个单块输出掩模方法，用于通过提供一种特殊的氧化方法来形成N沟道和P沟道MOS场效应晶体管，该氧化方法在已经形成的N +源极/漏极区上生长足够的氧化硅，其足以阻挡P + 离子注入，其从N沟道器件区域形成P沟道器件。

公开(公告)号：US20080191290A1

公开(公告)日：2008-08-14

申请号：US12012423

申请日：2008-01-31

Applicant: Geon-Ook Park

Inventor： Geon-Ook Park

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L29/42368 ,  Y10S148/163 ,  Y10S438/981

Abstract: Semiconductor devices and methods of manufacturing the same are disclosed. A disclosed semiconductor device comprises a semiconductor substrate; a gate formed on the semiconductor substrate; a gate oxide layer interposed between the semiconductor substrate and the gate; and source and drain regions formed within the substrate at opposite sides of the gate. The gate oxide layer has a first region with a first thickness and a second region with a second thickness. The second thickness is thicker than the first thickness.

Abstract translation: 公开了半导体器件及其制造方法。 所公开的半导体器件包括半导体衬底; 形成在半导体衬底上的栅极; 插入在半导体衬底和栅极之间的栅极氧化层; 以及在栅极的相对侧在衬底内形成的源极和漏极区域。 栅极氧化物层具有第一厚度的第一区域和具有第二厚度的第二区域。 第二厚度比第一厚度厚。

公开(公告)号：US20050130441A1

公开(公告)日：2005-06-16

申请号：US10981987

申请日：2004-11-05

Applicant: Geon-Ook Park

Inventor： Geon-Ook Park

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/43 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L29/42368 ,  Y10S148/163 ,  Y10S438/981

Abstract: Semiconductor devices and methods of manufacturing the same are disclosed. A disclosed semiconductor device comprises a semiconductor substrate; a gate formed on the semiconductor substrate; a gate oxide layer interposed between the semiconductor substrate and the gate; and source and drain regions formed within the substrate at opposite sides of the gate. The gate oxide layer has a first region with a first thickness and a second region with a second thickness. The second thickness is thicker than the first thickness.

Abstract translation: 公开了半导体器件及其制造方法。 所公开的半导体器件包括半导体衬底; 形成在半导体衬底上的栅极; 插入在半导体衬底和栅极之间的栅极氧化层; 以及在栅极的相对侧在衬底内形成的源极和漏极区域。 栅极氧化物层具有第一厚度的第一区域和具有第二厚度的第二区域。 第二厚度比第一厚度厚。

公开(公告)号：US06335262B1

公开(公告)日：2002-01-01

申请号：US09231617

申请日：1999-01-14

Applicant: Scott W. Crowder ,  Anthony Gene Domenicucci ,  Liang-Kai Han ,  Michael John Hargrove ,  Paul Andrew Ronsheim

Inventor： Scott W. Crowder ,  Anthony Gene Domenicucci ,  Liang-Kai Han ,  Michael John Hargrove ,  Paul Andrew Ronsheim

IPC: H01L2131

CPC classification number: H01L21/823462 ,  H01L21/31662 ,  Y10S148/116 ,  Y10S148/163 ,  Y10S438/981

Abstract: A semiconductor structure having silicon dioxide layers of different thicknesses is fabricated by forming a sacrificial silicon dioxide layer on the surface of a substrate; implanting nitrogen ions through the sacrificial silicon dioxide layer into first areas of the semiconductor substrate; implanting chlorine and/or bromine ions through the sacrificial silicon dioxide layer into second areas of the semiconductor substrate where silicon dioxide having the highest thickness is to be formed; removing the sacrificial silicon dioxide layer; and then growing a layer of silicon dioxide on the surface of the semiconductor substrate. The growth rate of the silicon dioxide will be faster in the areas containing the chlorine and/or bromine ions and therefore the silicon dioxide layer will be thicker in those regions as compared to the silicon dioxide layer in the regions not containing the chlorine and/or bromine ions. The growth rate of the silicon dioxide will be slower in the areas containing the nitrogen ions and therefore the silicon dioxide layer will be thinner in those regions as compared to the silicon dioxide layer in the regions not containing the nitrogen ions. Also provided are structures obtained by the above process.

Abstract translation: 通过在基板的表面上形成牺牲二氧化硅层来制造具有不同厚度的二氧化硅层的半导体结构; 将氮离子通过牺牲二氧化硅层注入到半导体衬底的第一区域中; 将氯和/或溴离子通过牺牲二氧化硅层注入到要形成具有最高厚度的二氧化硅的半导体衬底的第二区域中; 去除牺牲二氧化硅层; 然后在半导体衬底的表面上生长一层二氧化硅。 在含有氯和/或溴离子的区域中，二氧化硅的生长速度将更快，因此与不含氯和/或溴离子的区域中的二氧化硅层相比，二氧化硅层在这些区域中将更厚。 溴离子。 与含氮离子的区域相比，在含氮离子的区域中，二氧化硅的生长速度较慢，因此与这些区域的二氧化硅层相比，二氧化硅层较薄。 还提供了通过上述方法获得的结构。

公开(公告)号：US5679586A

公开(公告)日：1997-10-21

申请号：US138606

申请日：1993-10-14

Applicant: Richard Anthony Alexis Rodrigues ,  Ewen Gillespie

Inventor： Richard Anthony Alexis Rodrigues ,  Ewen Gillespie

IPC: H01L21/033 ,  H01L21/74 ,  H01L21/761 ,  H01L21/8222 ,  H01L21/265

CPC classification number: H01L21/761 ,  H01L21/033 ,  H01L21/743 ,  H01L21/8222 ,  Y10S148/01 ,  Y10S148/163

Abstract: This is a method of making a semiconductor device comprising covering a first semiconductor compound having a plurality of windows on a major surface of a semiconductor body, covering a second semiconductor compound on selected windows of the first compound, forming openings in the second compound over the selected windows, forming electrodes by introducing an impurity in the semiconductor body through the openings.

Abstract translation: 这是制造半导体器件的方法，其包括在半导体主体的主表面上覆盖具有多个窗口的第一半导体化合物，在第一化合物的选定窗口上覆盖第二半导体化合物，在第二化合物上形成开口 选择的窗口，通过在该半导体本体中引入杂质而形成电极。