公开(公告)号：US5371047A

公开(公告)日：1994-12-06

申请号：US968789

申请日：1992-10-30

申请人： Stephen E. Greco ,  Kris V. Srikrishnan

发明人： Stephen E. Greco ,  Kris V. Srikrishnan

IPC分类号： H01L21/768 ,  H01L23/12 ,  H01L23/29 ,  H01L23/522 ,  H01L23/532 ,  H01L21/90

CPC分类号： H01L23/293 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76829 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S148/043

摘要： An integrated circuit having organic dielectric between interconnection layers eliminates damage caused by vapors outgassing from the organic dielectric by the use of a two-component organic layer having a breathable etch resistant organic layer above the main organic dielectric layer, both of the organic layers remaining in the final circuit. The etch resistant layer is resistant to the etchant used to pattern the layer of interconnect above the organic dielectric.

摘要翻译： 在互连层之间具有有机电介质的集成电路通过使用在主有机电介质层上方具有透气的耐蚀刻有机层的双组分有机层消除由有机电介质释气引起的损害，两个有机层保留在 最后的电路。 耐蚀刻层对于用于对有机电介质上方的互连层进行图案化的蚀刻剂是耐受的。

公开(公告)号：US5210045A

公开(公告)日：1993-05-11

申请号：US862474

申请日：1992-05-18

申请人： George E. Possin ,  Harold G. Parks ,  Jack D. Kingsley

发明人： George E. Possin ,  Harold G. Parks ,  Jack D. Kingsley

IPC分类号： H01L27/12

CPC分类号： H01L27/12 ,  Y10S148/043 ,  Y10S438/98

摘要： A dual dielectric structure is employed in the fabrication of thin film field effect transistors in a matrix addressed liquid display to provide improved transistor device characteristics and also to provide both electrical and chemical isolation for material employed in the gate metallization layer. In particular, the use of a layer of silicon oxide over the gate metallization layer is not only consistent with providing the desired electrical and chemical isolation, but also with providing redundant gate metallization material to be employed beneath source or data lines for electrical circuit redundancy. Gate line redundancy is also possible. The electrical and chemical isolation provided by the dual dielectric layer reduces the possibilities of short circuits occurring in the display. The absence of short circuits together with the improved redundancy characteristics significantly increase manufacturing yield. As display sizes increase, the yield problem becomes more and more significant, generally growing as the square of the diagonal measurement of the screen. The structure in the present invention also significantly reduces gate leakage current. In the process and structure of the present invention, gate electrode material is separated from semiconductor material by the aforementioned dual dielectric, typically comprising layers of silicon oxide disposed beneath a layer of silicon nitride which is, in turn, disposed beneath the active amorphous silicon semiconductor material.

摘要翻译： 双电介质结构用于在矩阵寻址液体显示器中制造薄膜场效应晶体管以提供改进的晶体管器件特性，并且还为栅极金属化层中所采用的材料提供电和化学隔离。 特别地，在栅极金属化层上使用一层氧化硅不仅与提供期望的电和化学隔离一致，而且还提供要用于电路冗余的源极或数据线下方的冗余栅极金属化材料。 栅线冗余也是可能的。 由双电介质层提供的电气和化学隔离减少了在显示器中发生短路的可能性。 没有短路以及改进的冗余特性显着提高了制造产量。 随着显示尺寸的增加，产量问题变得越来越重要，通常随屏幕对角线测量的平方而增长。 本发明的结构也显着地降低了栅极漏电流。 在本发明的方法和结构中，栅极电极材料通过上述双电介质与半导体材料分离，所述双电介质通常包括设置在有源非晶硅半导体下方的氮化硅层下方的氧化硅层 材料。

公开(公告)号：US4966865A

公开(公告)日：1990-10-30

申请号：US245886

申请日：1988-09-16

申请人： Michael T. Welch ,  Ronald E. McMann ,  Manuel L. Torreno, Jr. ,  Evaristo Garcia, Jr. ,  Jeffrey E. Brighton

发明人： Michael T. Welch ,  Ronald E. McMann ,  Manuel L. Torreno, Jr. ,  Evaristo Garcia, Jr. ,  Jeffrey E. Brighton

IPC分类号： H01L21/3205 ,  H01L21/768

CPC分类号： H01L21/76819 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76877 ,  Y10S148/043

摘要： A method for planarizing a semiconductor slice prior to its metallization is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar. Contact vias are etched through the undoped and doped oxides; the silicide film acts as an etch stop, allowing contacts of differing depths to be etched from the planar top surface of the undoped oxide without etching through any of the polysilicon layers to which contact is to be made. A metal such as tungsten is deposited onto the slice to fill the contact vias, and is planarized in the same fashion as was the undoped oxide. The metallization is then sputtered onto the planar surface presented by the planarized undoped oxide and the planarized tungsten, and is patterned and etched to form the desired interconnection pattern.

摘要翻译： 公开了一种在其金属化之前对半导体薄片进行平坦化的方法。 处理半导体片以便使用公知的技术形成扩散和下面的互连层。 在金属化之前沉积和图案化最后的互连层之后，将铂或另一种金属层沉积在切片上。 将切片烧结以在直接暴露于溅射铂的互连层和扩散部分上形成硅化物膜。 然后沉积一层磷掺杂电介质，随后是一层未掺杂的氧化物。 将光致抗蚀剂或其他保形材料旋转到切片上，得到平坦的顶表面。 将切片暴露于等离子体蚀刻，其蚀刻光致抗蚀剂和未掺杂的氧化物，导致基本上为平面的未掺杂氧化物的顶表面。 接触孔通过未掺杂和掺杂的氧化物蚀刻; 硅化物膜用作蚀刻停止件，允许从未掺杂的氧化物的平坦顶表面蚀刻不同深度的接触，而不蚀刻通过要进行接触的任何多晶硅层。 将诸如钨的金属沉积在切片上以填充接触孔，并且以与未掺杂的氧化物相同的方式被平坦化。 然后将金属化溅射到由平坦化未掺杂的氧化物和平坦化钨呈现的平坦表面上，并被图案化和蚀刻以形成所需的互连图案。

公开(公告)号：US4960723A

公开(公告)日：1990-10-02

申请号：US330850

申请日：1989-03-30

申请人： Robert B. Davies

发明人： Robert B. Davies

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L21/60 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/66696 ,  H01L21/2255 ,  H01L29/41766 ,  Y10S148/043 ,  Y10S148/103 ,  Y10S148/126 ,  Y10S148/147 ,  Y10S257/90

摘要： An improved method for making a self-aligned vertical field effect transistor is provided wherein a nitride sidewall spacer is formed around a polysilicon gate, and an oxide sidewall spacer, which may be heavily doped with an n-type dopant, is formed covering the silicon nitride sidewall spacer. The silicon nitride sidewall spacer allows the oxide sidewall spacer of a conventional self-aligned vertical field effect transistor process to be removed partially or completely before making ohmic contact to the source thus increasing the contact area between the source and the source electrode and eliminating reliability problems related to n-type doped oxide in contact with aluminum electrodes.

摘要翻译： 提供一种用于制造自对准垂直场效应晶体管的改进方法，其中在多晶硅栅极周围形成氮化物侧壁间隔物，并且形成可以重掺杂n型掺杂剂的氧化物侧壁间隔物，覆盖硅 氮化物侧壁间隔物。 氮化硅侧壁间隔物允许在对源极进行欧姆接触之前部分或完全去除常规自对准垂直场效应晶体管工艺的氧化物侧壁间隔物，从而增加源极和源极之间的接触面积并消除可靠性问题 涉及与铝电极接触的n型掺杂氧化物。

公开(公告)号：US4795722A

公开(公告)日：1989-01-03

申请号：US10937

申请日：1987-02-05

申请人： Michael T. Welch ,  Ronald E. McMann ,  Manuel L. Torreno, Jr. ,  Evaristo Garcia, Jr. ,  Jeffrey E. Brighton

发明人： Michael T. Welch ,  Ronald E. McMann ,  Manuel L. Torreno, Jr. ,  Evaristo Garcia, Jr. ,  Jeffrey E. Brighton

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L21/90 ,  H01L23/48 ,  H01L29/46

CPC分类号： H01L21/76877 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76819 ,  Y10S148/011 ,  Y10S148/043 ,  Y10S148/133 ,  Y10S148/147

摘要： A method for planarizing a semiconductor slice prior to its metallization is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of the platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar. Contact vias are etched through the undoped and doped oxides; the silicide film acts as an etch stop, allowing contacts of differing depths to be etched from the planar top surface of the undoped oxide without etching through any of the polysilicon layers to which contact is to be made. A metal such as tungsten is deposited onto the slice to fill the contact vias, and is planarized in the same fashion as was the undoped oxide. The metallization is then sputtered onto the planar surface presented by the planarized undoped oxide and the planarized tungsten, and is patterned and etched to form the desired interconnection pattern.

摘要翻译： 公开了一种在其金属化之前对半导体薄片进行平坦化的方法。 处理半导体片以便使用公知的技术形成扩散和下面的互连层。 在金属化之前沉积和图案化最后的互连层之后，将铂或另一种金属层沉积在切片上。 将切片烧结以在直接暴露于溅射铂的互连层和扩散部分上形成硅化物膜。 然后沉积一层磷掺杂电介质，随后是一层未掺杂的氧化物。 将光致抗蚀剂或其他保形材料旋转到切片上，得到平坦的顶表面。 将切片暴露于等离子体蚀刻，其蚀刻光致抗蚀剂和未掺杂的氧化物，导致基本上为平面的未掺杂氧化物的顶表面。 接触孔通过未掺杂和掺杂的氧化物蚀刻; 硅化物膜用作蚀刻停止件，允许从未掺杂的氧化物的平坦顶表面蚀刻不同深度的接触，而不蚀刻通过要进行接触的任何多晶硅层。 将诸如钨的金属沉积在切片上以填充接触孔，并且以与未掺杂的氧化物相同的方式被平坦化。 然后将金属化溅射到由平坦化未掺杂的氧化物和平坦化钨呈现的平坦表面上，并被图案化和蚀刻以形成所需的互连图案。

公开(公告)号：US4621277A

公开(公告)日：1986-11-04

申请号：US372720

申请日：1982-04-28

申请人： Takashi Ito ,  Takao Nozaki

发明人： Takashi Ito ,  Takao Nozaki

IPC分类号： H01L21/28 ,  H01L21/314 ,  H01L21/318 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/51 ,  H01L29/34

CPC分类号： H01L21/28202 ,  H01L21/3144 ,  H01L21/3185 ,  H01L27/10805 ,  H01L27/1085 ,  H01L27/10873 ,  H01L29/51 ,  H01L29/511 ,  H01L21/28167 ,  Y10S148/043 ,  Y10S148/112 ,  Y10S148/114

摘要： An insulative film, such as SiO.sub.2, Si.sub.3 N.sub.4 and PSG films, is commonly used, for example, the passivation film or to insulate the gate electrode of MISFETs. Stability of the insulative films during the production or operation of the semiconductor devices is enhanced by providing an insulative film which is formed by nitridation, for example, in an NH.sub.3 gas, of an SiO.sub.2 film, preferably a directly thermally oxidized film of silicon. The insulative film according to the present invention is used for a gate insulation film in MISFETs, a capacitor or passivation film for semiconductor devices, and as a mask for selectively forming circuit elements of semiconductor devices. The process for forming the insulative film may comprise successive nitridation, oxidation and nitridation steps.

摘要翻译： 通常使用诸如SiO 2，Si 3 N 4和PSG膜的绝缘膜，例如钝化膜或使MISFET的栅电极绝缘。 通过提供通过例如在NH 3气体中形成SiO 2膜，优选直接热氧化的硅膜形成的绝缘膜来增强半导体器件的生产或操作期间的绝缘膜的稳定性。 根据本发明的绝缘膜用于MISFET中的栅极绝缘膜，用于半导体器件的电容器或钝化膜，以及用于选择性地形成半导体器件的电路元件的掩模。 形成绝缘膜的方法可以包括连续的氮化，氧化和氮化步骤。

公开(公告)号：US4192059A

公开(公告)日：1980-03-11

申请号：US913257

申请日：1978-06-06

申请人： Mahboob Khan ,  Gordon C. Godejahn, Jr. ,  Gary L. Heimbigner ,  Noubar A. Aghishian

发明人： Mahboob Khan ,  Gordon C. Godejahn, Jr. ,  Gary L. Heimbigner ,  Noubar A. Aghishian

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8247 ,  H01L23/52 ,  H01L27/088 ,  H01L27/112 ,  H01L29/788 ,  H01L29/792 ,  B01J17/00

CPC分类号： H01L21/76897 ,  H01L21/28 ,  H01L21/28525 ,  H01L27/112 ,  Y10S148/043 ,  Y10S148/116 ,  Y10S148/133 ,  Y10S148/141 ,  Y10S148/173

摘要： A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and self-aligned contacts for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different oxidation and etch characteristics permits selective oxidation of only desired portions of the structure without need for masking, and removal of selected material from desired locations by batch removal processes again without use of masking. The process and resulting structure affords inherently self-aligned gates and contacts for FET devices and conducting lines. Processing may employ conventional diffusion, oxidation, and etch techniques, although optional high energy ion implant techniques may be employed with simplification and reduction of process steps necessary for conventional diffusion techiques. Direct gate, source, drain, polysilicon line and diffused line contacts are provided. The reduction in size of individual elements and improved interconnection capabilities in accordance with the invention provide VLSI circuits having increased density and reliability.

摘要翻译： 用于制造VLSI（非常大规模集成的）电路的工艺采用用于FET器件的自对准栅极和触点的技术以及衬底中的两个扩散导线的自对准触点和位于衬底上形成的隔离场氧化物上的多晶硅导电线 。 掩模对准公差增加并呈现非关键性。 使用具有不同氧化和蚀刻特性的连续层中的材料允许仅选择性氧化结构的所需部分，而不需要掩蔽，并且通过再次分批除去工艺而不使用掩模从所需位置去除所选择的材料。 该工艺和结果为FET器件和导线提供了固有的自对准栅极和触点。 尽管可以采用可选的高能离子注入技术来简化和减少常规扩散技术所需的工艺步骤，但是处理可采用常规的扩散，氧化和蚀刻技术。 提供直接栅极，源极，漏极，多晶硅线和扩散线路触点。 根据本发明的单个元件的尺寸的减小和改进的互连能力提供了具有增加的密度和可靠性的VLSI电路。

公开(公告)号：US4110125A

公开(公告)日：1978-08-29

申请号：US773885

申请日：1977-03-03

申请人： Klaus Dietrich Beyer

发明人： Klaus Dietrich Beyer

IPC分类号： H01L21/033 ,  H01L21/314 ,  H01L29/08 ,  H01L21/95 ,  H01L21/74 ,  H01L21/76

CPC分类号： H01L29/0804 ,  H01L21/033 ,  H01L21/3144 ,  Y10S148/003 ,  Y10S148/033 ,  Y10S148/043 ,  Y10S148/085 ,  Y10S148/117 ,  Y10S148/131

摘要： A method for fabricating microminiature, planar semiconductor devices in which the number of defects, in particular, pipes, is minimized. The thicknesses of the thermally grown silicon dioxide and of the silicon nitride masking layers which are used for the formation of limited impurity regions by high temperature diffusion processes within the semiconductor substrate have a specified, limited range. The thickness of the silicon dioxide is between 800A - 3000A and the thickness of the silicon nitride is between around 250A and 600A, preferably 500A. The method is particularly useful in forming extremely small emitter regions in bipolar transistors.

摘要翻译： 一种制造微型平面半导体器件的方法，其中缺陷数量，特别是管道的数量最小化。 用于通过半导体衬底内的高温扩散工艺形成有限杂质区域的热生长二氧化硅和氮化硅掩蔽层的厚度具有规定的有限范围。 二氧化硅的厚度在800A至3000A之间，氮化硅的厚度在约250A至600A之间，优选为500A。 该方法在双极晶体管中形成极小的发射极区域特别有用。

公开(公告)号：US4023195A

公开(公告)日：1977-05-10

申请号：US653912

申请日：1976-01-30

申请人： Paul Richman

发明人： Paul Richman

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/41725 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/78 ,  Y10S148/043 ,  Y10S148/085 ,  Y10S148/117

摘要： An MOS field effect transistor includes a substrate in which source and drain regions are formed. A thick silicon dioxide layer is selectively formed on the upper surface of the substrate, so that in the resulting structure, the junction depth associated with the source and drain regions is selectively greater at contact locations and at the portions of the source and drain regions that are in contact with the active channel.

摘要翻译： MOS场效应晶体管包括其中形成源极和漏极区的衬底。 在衬底的上表面上选择性地形成厚的二氧化硅层，使得在所得到的结构中，与源极和漏极区域相关联的结深度在接触位置和源极和漏极区域的部分处选择性地较大， 与活动通道接触。

公开(公告)号：US3997368A

公开(公告)日：1976-12-14

申请号：US589945

申请日：1975-06-24

申请人： Pierre Marc Petroff ,  George Arthur Rozgonyi

发明人： Pierre Marc Petroff ,  George Arthur Rozgonyi

IPC分类号： H01L29/73 ,  H01L21/205 ,  H01L21/316 ,  H01L21/318 ,  H01L21/322 ,  H01L21/331 ,  H01L21/265

CPC分类号： H01L21/02178 ,  H01L21/0217 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/3162 ,  H01L21/3185 ,  H01L21/3221 ,  Y10S148/003 ,  Y10S148/043 ,  Y10S148/06 ,  Y10S148/061 ,  Y10S148/097 ,  Y10S438/928 ,  Y10S438/938

摘要： Described are procedures for fabricating silicon devices which prevent the formation and/or activation of stacking fault nucleation sites during high temperature processing steps, such as steam oxidation of silicon wafers. The procedures, which take place before such high temperature steps, include forming on the back surface of the wafer a stressed layer and then annealing the wafer for a time and at a temperature effective to cause the nucleation sites to diffuse to a localized region near to the back surface. Illustratively the stressed layer comprises silicon nitride or aluminum oxide. Enhanced gettering is achieved if, prior to forming the stressed layer, interfacial misfit dislocations are introduced into the back surface by, for example, diffusion of phosphorus therein. Following the gettering step(s) on the back surface, conventional procedures, such as growing epilayers and/or forming p-n junctions, are performed on the front surface of the wafer.

摘要翻译： 描述了在高温处理步骤（例如硅晶片的蒸汽氧化）期间制造硅器件的程序，其防止堆叠故障成核位置的形成和/或激活。 在这样的高温步骤之前进行的步骤包括在晶片的背面上形成应力层，然后在晶片上退火一段时间，并且有效地使成核部位扩散到靠近 背面。 说明性地，应力层包括氮化硅或氧化铝。 如果在形成应力层之前，通过例如其中的磷的扩散将界面失配位错引入背表面，则可实现增强的吸气。 在后表面上的吸气步骤之后，在晶片的前表面上执行诸如增长的外延层和/或形成p-n结的常规工艺。