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    Circuit structure having a matrix of active devices
    3.
    发明授权
    Circuit structure having a matrix of active devices 失效
    具有有源器件矩阵的电路结构

    公开(公告)号：US5942804A

    公开(公告)日：1999-08-24

    申请号：US697927

    申请日：1996-09-03

    Applicant: Clifford A. Mohwinkel ,  Mark Van Ness Faulkner

    Inventor： Clifford A. Mohwinkel ,  Mark Van Ness Faulkner

    IPC: H01L23/66 ,  H03F3/60 ,  H01L23/48 ,  H01L23/52 ,  H03C3/08 ,  H03C5/12

    CPC classification number: H03F3/604 ,  H01L23/66 ,  H01L2223/6644 ,  H01L2224/16 ,  H01L2924/1305 ,  H01L2924/3011 ,  H03F2200/372 ,  Y10S438/98

    Abstract: A means of connecting a plurality of essentially identical active devices is presented for the purpose of multifunction and multiple function operation. These devices, mounted on a chip, are flip-mounted to a circuit motherboard having large passive elements. A push-pull amplifier is presented as an example in which the multiple function operation is the combining of amplifiers whose active devices are on a single chip. The electromagnetic coupling, impedance matching and signal transmission are variously provided by the use of striplines, slotlines, coplanar waveguides, and a slotline converted into a coplanar waveguide.

    Abstract translation: 为了多功能和多功能操作的目的，提出了连接多个基本相同的有源设备的手段。 安装在芯片上的这些器件被翻转安装到具有大的无源元件的电路母板上。 以推挽放大器为例，其中多功能操作是其有源器件在单个芯片上的放大器的组合。 电磁耦合，阻抗匹配和信号传输通过使用带状线，缝合线，共面波导和转换成共面波导的槽线不同地提供。

    Method for continuously making a semiconductor device
    4.
    发明授权
    Method for continuously making a semiconductor device 失效
    连续制造半导体器件的方法

    公开(公告)号：US5753531A

    公开(公告)日：1998-05-19

    申请号：US660190

    申请日：1996-06-03

    Applicant: Jeffrey Frey

    Inventor： Jeffrey Frey

    IPC: H01L21/00 ,  H01L21/22

    CPC classification number: H01L21/67236 ,  H01L21/67092 ,  Y10S430/143 ,  Y10S438/907 ,  Y10S438/98

    Abstract: A method of continuous manufacture of semiconductor integrated circuits, said method and apparatus adapted to contain the semiconductor substrate, semiconductor deposition coating processes, and etching processes within a substantially collocated series of process chambers so that the semiconductor travels from one chamber to the next without exposure to airborne impurities and contact with manufacturing personnel. The invention has particular utility in the high volume fabrication of large surface area semiconductor circuits such as active matrix liquid crystal displays. The present invention contains a roll-to-roll and continuous belt embodiment.

    Abstract translation: 一种连续制造半导体集成电路的方法，所述方法和装置适于在基本上配置的一系列处理室内容纳半导体衬底，半导体淀积涂覆工艺和蚀刻工艺，使得半导体从一个室行进到下一个室而不暴露 与空气中的杂质和制造人员接触。 本发明在诸如有源矩阵液晶显示器的大面积半导体电路的大量制造中具有特别的用途。 本发明包括卷对卷和连续带实施例。

    Method for manufacturing semiconductor devices
    5.
    发明授权
    Method for manufacturing semiconductor devices 失效
    制造半导体器件的方法

    公开(公告)号：US5563095A

    公开(公告)日：1996-10-08

    申请号：US353206

    申请日：1994-12-01

    Applicant: Jeffrey Frey

    Inventor： Jeffrey Frey

    IPC: H01L21/00 ,  H01L21/22

    CPC classification number: H01L21/67236 ,  H01L21/67092 ,  Y10S430/143 ,  Y10S438/907 ,  Y10S438/98

    Abstract: A method of continuous manufacture of semiconductor integrated circuits, said method and apparatus adapted to contain the semiconductor substrate, semiconductor deposition coating processes, and etching processes within a substantially collocated series of process chambers so that the semiconductor travels from one chamber to the next without exposure to airborne impurities and contact with manufacturing personnel. The invention has particular utility in the high volume fabrication of large surface area semiconductor circuits such as active matrix liquid crystal displays. The present invention contains a roll-to-roll and continuous belt embodiment.

    Abstract translation: 一种连续制造半导体集成电路的方法，所述方法和装置适于在基本上配置的一系列处理室内容纳半导体衬底，半导体淀积涂覆工艺和蚀刻工艺，使得半导体从一个室行进到下一个室而不暴露 与空气中的杂质和制造人员接触。 本发明在诸如有源矩阵液晶显示器的大面积半导体电路的大量制造中具有特别的用途。 本发明包括卷对卷和连续带实施例。

    Computer-controlled individual chip management system for processing wafers
    6.
    发明授权
    Computer-controlled individual chip management system for processing wafers 失效
    用于处理晶圆的计算机控制的单片机管理系统

    公开(公告)号：US5448488A

    公开(公告)日：1995-09-05

    申请号：US202157

    申请日：1994-02-25

    Applicant: Takefumi Oshima

    Inventor： Takefumi Oshima

    IPC: B23Q41/00 ,  B65G61/00 ,  G05B15/02 ,  G05B19/418 ,  G06Q50/00 ,  G06Q50/04 ,  H01L21/02 ,  G05B19/18

    CPC classification number: G05B19/41865 ,  G05B2219/31428 ,  G05B2219/45026 ,  Y02P90/04 ,  Y02P90/20 ,  Y10S438/98

    Abstract: Chips formed on respective wafers are numbered. A map in which chip positions are correlated with chip numbers is created. A process is specified for each individual chip. A host computer creates processing information from inputted lot information for each individual chip and supplies the created processing information to a processing apparatus. A terminal for receiving various kinds of information, a line terminal, a processing information storage means for storing processing information, and a line interior information storage means are connected to the host computer. Also, a chip-managing computer is connected to the host computer. This chip-managing computer creates maps of chips formed on wafers and creates map information in which device information is correlated with chip numbers assigned to respective chips. A chip information storage means for storing the map information is connected to the chip-managing computer.

    Abstract translation: 编号在各晶片上形成的芯片。 创建芯片位置与芯片编号相关的图。 为每个单独的芯片指定一个过程。 主计算机从每个单独芯片的输入批量信息创建处理信息，并将所创建的处理信息提供给处理装置。 用于接收各种信息的终端，线路终端，用于存储处理信息的处理信息存储装置和线内信息存储装置连接到主计算机。 此外，芯片管理计算机连接到主计算机。 该芯片管理计算机创建在晶片上形成的芯片的映射，并创建映射信息，其中设备信息与分配给各个芯片的芯片编号相关联。 用于存储地图信息的芯片信息存储装置连接到芯片管理计算机。

    Method for fabricating a semiconductor device using implantation and subsequent annealing to eliminate defects
    7.
    发明授权
    Method for fabricating a semiconductor device using implantation and subsequent annealing to eliminate defects 失效
    使用注入和随后退火制造半导体器件以消除缺陷的方法

    公开(公告)号：US5407838A

    公开(公告)日：1995-04-18

    申请号：US196795

    申请日：1994-02-15

    Applicant: Tetsuya Ohnishi ,  Kazushi Naruse

    Inventor： Tetsuya Ohnishi ,  Kazushi Naruse

    IPC: H01L21/265 ,  H01L21/331 ,  H01L29/73 ,  H01L29/732

    CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L29/66272 ,  Y10S148/024 ,  Y10S438/966 ,  Y10S438/98

    Abstract: A method for fabricating a semiconductor device including carrying out an ion implantation into a predetermined region of a single-crystal silicon substrate to form therein an amorphized ion-implanted layer according to any one of the methods: (A) implanting an ion of an atom serving as carrier into the predetermined region, followed by implanting an ion of an electrically inert atom or molecule into the region, (B) implanting an ion of an electrically inert atom or molecule in the region, followed by implanting an ion of an atom serving as carrier in the region, and (C) implanting an ion of a molecule in which an atom serving as carrier is bonded to an electrically inert atom; annealing the substrate in an inert atmosphere to crystallize the amorphized ion-implanted layer again; and further annealing the substrate in an oxidizing atmosphere to eliminate defects at the interface of the substrate and the ion implantation layer.

    Abstract translation: 一种用于制造半导体器件的方法，包括根据以下方法中的任一种方法将离子注入到单晶硅衬底的预定区域中以形成非晶化离子注入层：（A）注入原子离子 作为载体进入预定区域，然后将电惰性原子或分子的离子注入该区域，（B）在该区域中注入电惰性原子或分子的离子，随后注入一个原子的离子 作为该区域的载体，（C）将其中作为载体的原子键合的分子的离子注入到电惰性的原子上; 在惰性气氛中对衬底退火，再次使非晶化离子注入层结晶; 并且在氧化气氛中进一步退火衬底以消除衬底和离子注入层的界面处的缺陷。

    Si/Au/Ni alloyed ohmic contact to n-GaAs and fabricating process therefor
    8.
    发明授权
    Si/Au/Ni alloyed ohmic contact to n-GaAs and fabricating process therefor 失效
    Si / Au / Ni合金欧姆接触到n-GaAs并制造工艺

    公开(公告)号：US5063174A

    公开(公告)日：1991-11-05

    申请号：US585015

    申请日：1990-09-18

    Applicant: Dana M. Beyea ,  Kathleen Meehan

    Inventor： Dana M. Beyea ,  Kathleen Meehan

    IPC: H01L21/28 ,  H01L21/285

    CPC classification number: H01L21/28 ,  H01L21/28575 ,  Y10S148/02 ,  Y10S438/98

    Abstract: An improved alloyed ohmic contact to n-type GaAs is provided utilizing a Si-based metallization of Si/Au/Ni and exhibiting low contact resistivity and high thermal stability. An improved process for fabricating the inventive contact is also provided comprising the step of first depositing the Si film on the GaAs substrate, thereby simplifying the fabrication of monolithically integrated devices, particularly advanced electro-optic devices, by incorporating self-aligned Si-based contacts in the process. A further improvement is provided in the use of a lift-off-defined Si layer as a reactive-ion etch mask to serve as the self-aligned contact in the process, thereby eliminating a critical photolithographic step of aligning the contact metallization.

    Abstract translation: 使用Si / Au / Ni的Si基金属化并且具有低接触电阻率和高热稳定性来提供与n型GaAs的改进的合金欧姆接触。 还提供了用于制造本发明接触的改进方法，其包括首先在GaAs衬底上沉积Si膜的步骤，从而通过结合自对准的Si基触点来简化单片集成器件，特别是先进的电光器件的制造 正在进行中。 在使用剥离定义的Si层作为反应离子蚀刻掩模的过程中提供了进一步的改进，以用作该过程中的自对准接触，从而消除了对准接触金属化的临界光刻步骤。

    Semiconductor laser
    9.
    发明授权
    Semiconductor laser 失效
    半导体激光器

    公开(公告)号：US4951289A

    公开(公告)日：1990-08-21

    申请号：US310370

    申请日：1989-02-13

    Applicant: Akihiro Shima

    Inventor： Akihiro Shima

    IPC: H01S5/00 ,  H01S5/223 ,  H01S5/24

    CPC classification number: H01S5/24 ,  H01S5/2237 ,  Y10S148/026 ,  Y10S148/095 ,  Y10S438/98

    Abstract: A semiconductor laser includes, serially disposed, a semiconductor substrate of a first conductivity type, a semiconductor current blocking layer of a second conductivity type opposite the first conductivity type, a first semiconductor cladding layer of the first conductivity type, an active semiconductor layer, a second semiconductor cladding layer of the second conductivity type, and a semiconductor contacting layer of the second conductivity type, and a structure for laterally confining the transverse flow of electrical current through the layers, the structure including a portion of the first cladding layer being disposed in a longitudinal groove extending through the current blocking layer into the substrate and high resistance longitudinal stripes disposed adjacent the groove between the second cladding layer and the current blocking layer, the high resistance stripes forming discontinuities in the active semiconductor layer.

    Abstract translation: 半导体激光器包括：串联设置的第一导电类型的半导体衬底，与第一导电类型相反的第二导电类型的半导体电流阻挡层，第一导电类型的第一半导体包覆层，有源半导体层， 第二导电类型的第二半导体包覆层和第二导电类型的半导体接触层，以及用于横向限制通过层的电流的横向流动的结构，该结构包括第一包层的一部分设置在 延伸穿过电流阻挡层进入衬底的纵向沟槽和与第二覆盖层和电流阻挡层之间的沟槽相邻设置的高电阻纵向条纹，该高电阻条纹形成有源半导体层中的不连续性。

    Method of making three dimensional structures of active and passive semiconductor components
    10.
    发明授权
    Method of making three dimensional structures of active and passive semiconductor components 失效
    制作有源和无源半导体元件三维结构的方法

    公开(公告)号：US4737470A

    公开(公告)日：1988-04-12

    申请号：US907184

    申请日：1986-09-12

    Applicant: Kenneth E. Bean

    Inventor： Kenneth E. Bean

    IPC: H01L21/822 ,  H01L27/06 ,  H01L21/302

    CPC classification number: H01L21/8221 ,  H01L27/0688 ,  Y10S148/164 ,  Y10S438/973 ,  Y10S438/98

    Abstract: The disclosure relates to a three dimensional semiconductor structure formed in a semiconductor substrate wherein electrical components, both active and passive, are formed on the substrate surface as well as in grooves formed in the substrate at an angle and extending to the surface. The substrate surface is designed to lie in a predetermined crystallographic plane of the substrate material and the grooves extend in a predetermined crystallographic direction from said plane, this being accomplished by orientation dependent etching.

    Abstract translation: 本公开涉及形成在半导体衬底中的三维半导体结构，其中有源和无源的电子部件形成在衬底表面上以及形成在衬底中的以一定角度并延伸到表面的凹槽中。 衬底表面设计成位于衬底材料的预定结晶平面中，并且沟槽从所述平面以预定的晶体方向延伸，这是通过取向相关蚀刻来实现的。

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