公开(公告)号：US4050979A

公开(公告)日：1977-09-27

申请号：US649130

申请日：1976-01-14

Applicant: Ronald K. Smeltzer ,  Kenneth E. Bean

Inventor： Ronald K. Smeltzer ,  Kenneth E. Bean

IPC: H01L21/306 ,  H01L21/762

CPC classification number: H01L21/30608 ,  H01L21/76297 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/15 ,  Y10S438/977

Abstract: This disclosure relates to methods of producing thin layers of silicon as well as thin layers of silicon on insulating substrates such as silicon dioxide or polycrystalline silicon by forming either an n- layer of single crystal silicon over a p++ layer of single crystal silicon or a p- layer of single crystal silicon over an n++ layer of single crystal silicon and then removing either the n++ or p++ single crystal substrate, as the case may be, by utilizing an etch which will only etch the n++ or p++ region and will stop when the n- or p- region, as the case may be, has been reached.

Abstract translation: 本公开涉及通过在p ++层的单晶硅或p上形成单晶硅的n层，在绝缘衬底例如二氧化硅或多晶硅上制造硅薄层以及薄层的硅的方法 - 单层硅单层硅层，然后通过使用仅蚀刻n ++或p ++区域的蚀刻去除n ++或p ++单晶衬底（视情况而定），并且将在 根据情况可以达到n-或p-区。

公开(公告)号：US5196378A

公开(公告)日：1993-03-23

申请号：US679122

申请日：1991-03-25

Applicant: Kenneth E. Bean ,  John Powell ,  Jack W. Freeman ,  Robert D. McGrath

Inventor： Kenneth E. Bean ,  John Powell ,  Jack W. Freeman ,  Robert D. McGrath

IPC: H01L21/306 ,  H01L21/78

CPC classification number: H01L21/78 ,  H01L21/30608 ,  Y10S148/028 ,  Y10S148/168

Abstract: The invention relates to a method of scribing and separating dice from each other after fabrication in a semiconductor wafer in a manner such that active circuit regions in the dice reside as near to an edge of a die as possible. The wafer is anistropically etched through the active layer and into the substrate through an opening in the mask to form a generally V-shaped channel with the dice then being separated along a vertex of the channel. The dice are then positioned to abut each other in the form of a mosaic.

Abstract translation: 本发明涉及一种在半导体晶片制造之后将骰子彼此划线并分离的方法，使得骰子中的有源电路区域尽可能靠​​近模具的边缘。 晶片通过有源层通过掩模中的开口被人造地蚀刻，并通过掩模中的开口形成大致V形的通道，然后沿着通道的顶点分离晶片。 然后将骰子定位成以马赛克的形式彼此邻接。

公开(公告)号：US4663648A

公开(公告)日：1987-05-05

申请号：US684197

申请日：1984-12-19

Applicant: Kenneth E. Bean

Inventor： Kenneth E. Bean

IPC: H01L21/822 ,  H01L27/06 ,  H01L21/42 ,  H01L21/461 ,  H01L29/04

CPC classification number: H01L27/0688 ,  H01L21/8221

Abstract: The disclosure relates to a three dimensional semiconductor structure formed in a semiconductor substrate wherein electrical components, both active and passive, are formed on the substrate surface as well as in grooves formed in the substrate at an angle and extending to the surface. The substrate surface is designed to lie in a predetermined crystallographic plane of the substrate material and the grooves extend in a predetermined crystallographic direction from said plane, this being accomplished by orientation dependent etching.

Abstract translation: 本公开涉及形成在半导体衬底中的三维半导体结构，其中有源和无源的电子部件形成在衬底表面上以及形成在衬底中的以一定角度延伸并延伸到表面的凹槽中。 衬底表面设计成位于衬底材料的预定结晶平面中，并且沟槽从所述平面以预定的晶体方向延伸，这是通过取向相关的蚀刻来实现的。

公开(公告)号：US3936929A

公开(公告)日：1976-02-10

申请号：US483264

申请日：1974-06-26

Applicant: Kenneth E. Bean ,  William W. Lloyd

Inventor： Kenneth E. Bean ,  William W. Lloyd

IPC: H01L21/762 ,  H01L21/764 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/00 ,  B01J17/00

CPC classification number: H01L27/0623 ,  H01L21/76264 ,  H01L21/764 ,  H01L21/8248 ,  H01L21/8249 ,  H01L29/00 ,  H01L21/76289 ,  Y10S148/051 ,  Y10S148/053 ,  Y10S148/085 ,  Y10S148/102 ,  Y10S148/145

Abstract: Disclosed are improved field-effect and bipolar semiconductor devices and the method of making them, wherein maximum junction control provides highly predictable device parameters. Low temperature epitaxial depositions provide tight junction thickness and resistivity control, and an orientation dependent etch forms grooves circumscribing portions of the host substrate and overlying epitaxial layers to provide dielectrically isolated single crystalline mesas utilized in forming electronic devices.This is a division of application Ser. No. 275,116, filed July 26, 1972.

Abstract translation: 公开了改进的场效应和双极半导体器件及其制造方法，其中最大接点控制提供高度可预测的器件参数。 低温外延沉积提供紧密的结厚度和电阻率控制，并且取向依赖的蚀刻形成限定主体衬底和上覆外延层的部分的凹槽，以提供用于形成电子器件的介电隔离的单晶台面。

公开(公告)号：US5089428A

公开(公告)日：1992-02-18

申请号：US457673

申请日：1989-12-27

Applicant: Douglas P. Verret ,  Kenneth E. Bean

Inventor： Douglas P. Verret ,  Kenneth E. Bean

IPC: H01L21/20 ,  H01L21/316 ,  H01L21/331 ,  H01L29/737

CPC classification number: H01L29/7378 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/31662 ,  H01L29/66242 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02664 ,  Y10S148/011 ,  Y10S148/059

Abstract: A method for preparing a germanium layer (22) adjacent to a germanium silicon layer (20). Initially, a P-germanium silicon layer (16) is deposited on to an N-germanium silicon layer (14). The continuous germanium layer (22) is formed by heating the layers (14 and 16) in a steam oxidation step to approximately 1000 degrees Centigrade to transform the P-germanium silicon layer (16) into the P-germanium layer (18) and a SiO.sub.2 layer (22). A method for forming a heterojunction bipolar transistor utilizing a P-germanium layer (50) is also disclosed.

公开(公告)号：US4922378A

公开(公告)日：1990-05-01

申请号：US893770

申请日：1986-08-01

Applicant: Satwinder S. Malhi ,  Kenneth E. Bean

Inventor： Satwinder S. Malhi ,  Kenneth E. Bean

IPC: H01L23/13 ,  H01L23/14 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/147 ,  H01L23/538 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/0002

Abstract: A baseboard for orthogonal mounting of integrated circuit chips is described. Plural channels (14) are anisotropically etched in a silicon baseboard (10). A corresponding plurality of integrated circuit chips (12) are inserted into the channels (14). A number of baseboard contact pads (18) are formed adjacent each channel (14), and are solder bonded to corresponding chip conductor pads (16). Interconnect conductors (20, 28) provide connection of each baseboard pad (18) either to other chips (12) or to connector pads (22) located adjacent an edge (26) of the baseboard chip mount (10). A coating (30) of silicon carbide over the surface of the baseboard chip mount (10) improves the thermal efficiency of the assembly.

Abstract translation: 描述了用于集成电路芯片的正交安装的基板。 在硅基板（10）中各向异性地蚀刻多个通道（14）。 相应的多个集成电路芯片（12）插入通道（14）中。 在每个通道（14）附近形成有多个基板接触焊盘（18），并焊接到相应的芯片导体焊盘（16）上。 互连导体（20,28）提供每个基板焊盘（18）与其它芯片（12）或邻近基板芯片安装架（10）的边缘（26）定位的连接器焊盘（22）的连接。 在基板芯片安装件（10）的表面上的碳化硅涂层（30）提高了组件的热效率。

公开(公告)号：US3969749A

公开(公告)日：1976-07-13

申请号：US578451

申请日：1975-05-19

Applicant: Kenneth E. Bean

Inventor： Kenneth E. Bean

IPC: H01L21/306 ,  H01L21/762 ,  H01L27/04 ,  H01L27/12

CPC classification number: H01L21/76297 ,  H01L21/30608

Abstract: Process permitting control of the thickness of the thin layer of semiconductor material by first forming a slot of a predetermined depth in one surface so that the slot will be exposed during removal of material from the opposite surface should the thickness of the thin layer of semiconductor material become less than the depth of the slot, and a (110) oriented semiconductor substrate having a slot formed therein which is bounded by converging {111} planes.In a preferred embodiment the thickness control is realized by first preparing the slice of semiconductor material so that at least one of its surfaces has a (100) orientation. There is then formed on the surface of the slice having the (100) orientation an etch-resistant mask having a window opened therethrough such that the window defines on the surface of the slice two lines which are parallel to each other and to lines defined by the intersection of {111} planes with the surface of the slice. Semiconductor material is then removed through the windows by etching to produce a slot having a depth greater than thickness to which the single crystal semiconductor material is to be subsequently processed. A vapor deposited support layer may then be produced on the surface of the slice to which the mask was attached during which process it will fill the slot etched in the semiconductor material through the window. Upon removal of the semiconductor material from the opposite surface of the slice, which may be affected by lapping and polishing, the support layer formed in the slot will become exposed, thus indicating that the thickness of the semiconductor material remaining is equal to or less than the depth of the slot etched in the first surface of the semiconductor material. At the time the first depth control slot is formed in the first surface of the semiconductor slice, there may also be performed a plurality of similar slots, the depth of which are controlled by controlling the width of the window in the etch resistant mask. Thus, as semiconductor material is removed from the slice, the thickness of the material remaining after the removal process can be determined by the number of slots exposed during lapping and polishing.

Abstract translation: 工艺允许通过首先在一个表面上形成预定深度的槽来控制半导体材料薄层的厚度，使得如果半导体材料薄层的厚度应该从相对表面去除材料期间露出槽 变得小于槽的深度，并且其中形成有槽的（110）取向的半导体衬底由{111}平面收敛而界定。

公开(公告)号：US5031072A

公开(公告)日：1991-07-09

申请号：US472698

申请日：1990-01-31

Applicant: Satwinder S. Malhi ,  Kenneth E. Bean

Inventor： Satwinder S. Malhi ,  Kenneth E. Bean

IPC: H01L23/13 ,  H01L23/14 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/13 ,  H01L23/147 ,  H01L23/538 ,  H01L25/0657 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/0002

Abstract: A baseboard for orthogonal mounting of integrated circuit chips thereto is described. Plural channels (14) are anisotropically etched in a silicon baseboard (10). A corresponding plurality of integrated circuit chips (12) are inserted into the channels (14). A number of baseboard contact pads (18) are formed adjacent each channel (14), and are solder bonded to corresponding chip conductor pads (16). Interconnect conductors (20, 28) provide connection of each baseboard pad (18) either to other chips (12) or to connector pads (22) located adjacent an edge (26) of the baseboard chip mount (10). A coating (30) of silicon carbide over the surface of the baseboard chip mount (10) improves the thermal efficiency of the assembly.

Abstract translation: 描述了用于将集成电路芯片正交安装的基板。 在硅基板（10）中各向异性地蚀刻多个通道（14）。 相应的多个集成电路芯片（12）插入通道（14）中。 在每个通道（14）附近形成有多个基板接触焊盘（18），并焊接到相应的芯片导体焊盘（16）上。 互连导体（20,28）提供每个基板焊盘（18）与其它芯片（12）或邻近基板芯片安装架（10）的边缘（26）定位的连接器焊盘（22）的连接。 在基板芯片安装件（10）的表面上的碳化硅涂层（30）提高了组件的热效率。

公开(公告)号：US4982263A

公开(公告)日：1991-01-01

申请号：US321612

申请日：1989-03-10

Applicant: David B. Spratt ,  Eldon J. Zorinsky ,  Robert L. Virkus ,  Kenneth E. Bean ,  Richard L. Yeakley

Inventor： David B. Spratt ,  Eldon J. Zorinsky ,  Robert L. Virkus ,  Kenneth E. Bean ,  Richard L. Yeakley

IPC: H01L21/20 ,  H01L21/762

CPC classification number: H01L21/76264 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/7627 ,  H01L21/76283 ,  Y10S438/938 ,  Y10S438/96

Abstract: A silicon on insulator semiconductor structure employs a strain layer fabricated of an electrically inactive material. The strain layer comprises silicon with a germanium additive to produce a sublayer exhibiting a low breakdown voltage and thus effective for selective anodization.

Abstract translation: 绝缘体上硅半导体结构采用由电惰性材料制成的应变层。 应变层包括具有锗添加剂的硅以产生显示低击穿电压的子层，因此对于选择性阳极氧化是有效的。

公开(公告)号：US4849370A

公开(公告)日：1989-07-18

申请号：US136225

申请日：1987-12-21

Applicant: David B. Spratt ,  Eldon J. Zorinsky ,  Robert L. Virkus ,  Kenneth E. Bean ,  Richard L. Yeakley

Inventor： David B. Spratt ,  Eldon J. Zorinsky ,  Robert L. Virkus ,  Kenneth E. Bean ,  Richard L. Yeakley

IPC: H01L21/20 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12

CPC classification number: H01L21/76264 ,  H01L21/7627 ,  H01L21/76283

Abstract: A silicon on insulator semiconductor structure employs a strain layer fabricated of an electrically inactive material. The strain layer comprises silicon with a germanium additive to produce a sublayer exhibiting a low breakdown voltage and thus effective for selective anodization.

Abstract translation: 绝缘体上硅半导体结构采用由电惰性材料制成的应变层。 应变层包括具有锗添加剂的硅以产生显示低击穿电压的子层，因此对于选择性阳极氧化是有效的。