公开(公告)号：US20170184892A1

公开(公告)日：2017-06-29

申请号：US15309499

申请日：2016-03-07

申请人： BOE TECHNOLOGY GROUP CO., LTD.

发明人： Zheng LIU

IPC分类号： G02F1/1368 ,  H01L27/12 ,  H01L21/265 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/167 ,  G02F1/1343 ,  H01L29/786

CPC分类号： G02F1/1368 ,  G02F1/134309 ,  G02F1/13439 ,  G02F2001/13685 ,  H01L21/26513 ,  H01L27/1255 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/167 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78675 ,  H01L2029/7863

摘要： A method for manufacturing an array substrate, including steps of forming a semiconductor pattern, a gate electrode and a first insulation pattern sequentially on a base substrate at different layers, an orthogonal projection of the semiconductor pattern onto the base substrate covering an orthogonal projection of the first insulation pattern onto the base substrate, and the orthogonal projection of the first insulation pattern onto the base substrate covering an orthogonal projection of the gate electrode onto the base substrate, and subjecting the semiconductor pattern to ion implantation through a single ion implantation process using the first insulation pattern and the gate electrode as a mask plate, so as to form an active layer, a heavily-doped source electrode region, a lightly-doped source electrode region, a heavily-doped drain electrode region, and a lightly-doped drain electrode region.

公开(公告)号：US09627460B2

公开(公告)日：2017-04-18

申请号：US14621668

申请日：2015-02-13

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki

IPC分类号： H01L27/32 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  H01L51/52

CPC分类号： H01L27/3262 ,  H01L21/28114 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/3244 ,  H01L27/3248 ,  H01L29/42384 ,  H01L29/66492 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78675 ,  H01L29/78696 ,  H01L51/5256 ,  H01L2029/7863 ,  H01L2227/32

摘要： There is provided a thin film transistor having improved reliability. A gate electrode includes a first gate electrode having a taper portion and a second gate electrode with a width narrower than the first gate electrode. A semiconductor layer is doped with phosphorus of a low concentration through the first gate electrode. In the semiconductor layer, two kinds of n−-type impurity regions are formed between a channel formation region and n+-type impurity regions. Some of the n−-type impurity regions overlap with a gate electrode, and the other n−-type impurity regions do not overlap with the gate electrode. Since the two kinds of n−-type impurity regions are formed, an off current can be reduced, and deterioration of characteristics can be suppressed.

公开(公告)号：US09601525B2

公开(公告)日：2017-03-21

申请号：US15098473

申请日：2016-04-14

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Hajime Kimura

IPC分类号： H01L29/04 ,  H01L27/12 ,  H01L27/32 ,  H01L29/66 ,  H01L29/786 ,  H01L27/06 ,  G02F1/1345

CPC分类号： H01L27/1255 ,  G02F1/13454 ,  H01L27/0629 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1262 ,  H01L27/3262 ,  H01L27/3265 ,  H01L27/3272 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78648 ,  H01L2029/7863

摘要： Solved is a problem of attenuation of output amplitude due to a threshold value of a TFT when manufacturing a circuit with TFTs of a single polarity. In a capacitor (105), a charge equivalent to a threshold value of a TFT (104) is stored. When a signal is inputted thereto, the threshold value stored in the capacitor (105) is added to a potential of the input signal. The thus obtained potential is applied to a gate electrode of a TFT (101). Therefore, it is possible to obtain the output having a normal amplitude from an output terminal (Out) without causing the amplitude attenuation in the TFT (101).

公开(公告)号：US09530799B2

公开(公告)日：2016-12-27

申请号：US14345344

申请日：2013-11-11

申请人： ORDOS YUANSHENG OPTOELECTRONICS CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

发明人： Zuqiang Wang

IPC分类号： H01L29/04 ,  H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66

CPC分类号： H01L27/1222 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/26513 ,  H01L21/324 ,  H01L27/127 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78675 ,  H01L2029/7863

摘要： A polysilicon thin film transistor, a manufacturing method thereof, an array substrate involve display technology field, and can repair the boundary defect and the defect state in polysilicon, suppress the hot carrier effect and make the characteristics of TFTs more stable. The polysilicon thin film transistor includes a gate electrode, a source electrode, a drain electrode and an active layer, the active layer comprises at least a channel area, first doped regions, second doped regions and heavily doped regions, and the first doped regions are disposed on two sides of the channel area, the second doped regions are disposed on sides of the first doped regions away from the channel area; the heavily doped regions are disposed on sides of the second doped regions opposed to the first doped regions; and dosage of ions in the heavily doped regions lies between that in the first doped regions and that in the second doped regions.

摘要翻译： 多晶硅薄膜晶体管及其制造方法，阵列基板涉及显示技术领域，可以修复多晶硅中的边界缺陷和缺陷状态，抑制热载流子效应，使TFT的特性更加稳定。 多晶硅薄膜晶体管包括栅电极，源电极，漏电极和有源层，有源层至少包括沟道区，第一掺杂区，第二掺杂区和重掺杂区，第一掺杂区是 设置在通道区域的两侧，第二掺杂区域设置在远离通道区域的第一掺杂区域的侧面上; 重掺杂区域设置在与第一掺杂区域相对的第二掺杂区域的侧面上; 并且重掺杂区域中的离子的剂量位于第一掺杂区域和第二掺杂区域中的离子剂量。

公开(公告)号：US20160282658A1

公开(公告)日：2016-09-29

申请号：US15181590

申请日：2016-06-14

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Yoshiharu HIRAKATA ,  Yuugo GOTO ,  Yuko KOBAYASHI ,  Shunpei YAMAZAKI

IPC分类号： G02F1/1339 ,  G02F1/1333 ,  G02F1/1335 ,  G02F1/1341 ,  H01L29/167 ,  G02F1/1368 ,  G02F1/1345 ,  H01L27/12 ,  H01L29/786 ,  G02F1/133 ,  G02F1/1343

CPC分类号： G02F1/13394 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/13338 ,  G02F1/133512 ,  G02F1/1341 ,  G02F1/134309 ,  G02F1/13454 ,  G02F1/1368 ,  G02F2001/133302 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/167 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78669 ,  H01L2029/7863 ,  H01L2924/0002 ,  Y10S438/924 ,  Y10S438/98 ,  H01L2924/00

摘要： There is provided a high quality liquid crystal panel having a thickness with high accuracy, which is designed, without using a particulate spacer, within a free range in accordance with characteristics of a used liquid crystal and a driving method, and is also provided a method of fabricating the same. The shape of a spacer for keeping a substrate interval constant is made such that it is a columnar shape, a radius R of curvature is 2 μm or less, a height H is 0.5 μm to 10 μm, a diameter is 20 μm or less, and an angle α is 65° to 115°. By doing so, it is possible to prevent the lowering of an opening rate and the lowering of light leakage due to orientation disturbance.

摘要翻译： 提供了具有高精度的高质量液晶面板，其根据所使用的液晶的特性和驱动方法在自由范围内设计而不使用颗粒间隔物，并且还提供了一种方法 的制造。 使基板间隔保持一定的间隔物的形状为圆柱状，曲率半径R为2μm以下，高度H为0.5μm〜10μm，直径为20μm以下， 角度α为65°〜115°。 通过这样做，可以防止打开速度的降低和由于取向干扰引起的光泄漏的降低。

公开(公告)号：US20150187953A1

公开(公告)日：2015-07-02

申请号：US14582273

申请日：2014-12-24

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Junichi Koezuka ,  Masami Jintyou ,  Yukinori Shima ,  Takashi Hamochi ,  Yasutaka Nakazawa ,  Shunpei Yamazaki

IPC分类号： H01L29/786 ,  H01L29/417 ,  H01L27/12 ,  H01L29/40 ,  H01L29/04

CPC分类号： H01L29/78696 ,  H01L27/1225 ,  H01L27/3262 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/7869 ,  H01L2029/7863

摘要： A novel semiconductor device including an oxide semiconductor is provided. In particular, a planar semiconductor device including an oxide semiconductor is provided. A semiconductor device including an oxide semiconductor and having large on-state current is provided. The semiconductor device includes an oxide insulating film, an oxide semiconductor film over the oxide insulating film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a gate insulating film between the source electrode and the drain electrode, and a gate electrode overlapping the oxide semiconductor film with the gate insulating film. The oxide semiconductor film includes a first region overlapped with the gate electrode and a second region not overlapped with the gate electrode, the source electrode, and the drain electrode. The first region and the second region have different impurity element concentrations. The gate electrode, the source electrode, and the drain electrode contain the same metal element.

摘要翻译： 提供了包括氧化物半导体的新型半导体器件。 特别地，提供了包括氧化物半导体的平面半导体器件。 提供包括氧化物半导体并具有大导通电流的半导体器件。 半导体器件包括氧化物绝缘膜，氧化物绝缘膜上的氧化物半导体膜，与氧化物半导体膜接触的源极和漏电极，源极和漏极之间的栅极绝缘膜，以及栅极 电极与氧化物半导体膜与栅极绝缘膜重叠。 氧化物半导体膜包括与栅电极重叠的第一区域和不与栅电极，源电极和漏电极重叠的第二区域。 第一区和第二区具有不同的杂质元素浓度。 栅电极，源电极和漏电极含有相同的金属元素。

公开(公告)号：US09069215B2

公开(公告)日：2015-06-30

申请号：US12556135

申请日：2009-09-09

申请人： Yoshiharu Hirakata ,  Yuugo Goto ,  Yuko Kobayashi ,  Shunpei Yamazaki

发明人： Yoshiharu Hirakata ,  Yuugo Goto ,  Yuko Kobayashi ,  Shunpei Yamazaki

IPC分类号： H01L27/14 ,  H01L29/04 ,  H01L29/15 ,  H01L31/036 ,  G02F1/1339 ,  H01L29/786 ,  G02F1/1333 ,  G02F1/1345

CPC分类号： G02F1/13394 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/13338 ,  G02F1/133512 ,  G02F1/1341 ,  G02F1/134309 ,  G02F1/13454 ,  G02F1/1368 ,  G02F2001/133302 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/167 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78669 ,  H01L2029/7863 ,  H01L2924/0002 ,  Y10S438/924 ,  Y10S438/98 ,  H01L2924/00

摘要： There is provided a high quality liquid crystal panel having a thickness with high accuracy, which is designed, without using a particulate spacer, within a free range in accordance with characteristics of a used liquid crystal and a driving method, and is also provided a method of fabricating the same. The shape of a spacer for keeping a substrate interval constant is made such that it is a columnar shape, a radius R of curvature is 2 μm or less, a height H is 0.5 μm to 10 μm, a diameter is 20 μm or less, and an angle α is 65° to 115°. By doing so, it is possible to prevent the lowering of an opening rate and the lowering of light leakage due to orientation disturbance.

公开(公告)号：US09047815B2

公开(公告)日：2015-06-02

申请号：US12708057

申请日：2010-02-18

申请人： Hajime Kimura

发明人： Hajime Kimura

IPC分类号： G09G5/10 ,  G09G3/32

CPC分类号： H01L29/78621 ,  G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0251 ,  G09G2310/0262 ,  G09G2320/043 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L2029/7863

摘要： To provide a method for driving a semiconductor device, by which influence of variation in threshold voltage and mobility of transistors can be reduced. The semiconductor device includes an n-channel transistor, a switch for controlling electrical connection between a gate and a first terminal of the transistor, a capacitor electrically connected between the gate and a second terminal of the transistor, and a display element. The method has a first period for holding the sum of a voltage corresponding to the threshold voltage of the transistor and an image signal voltage in the capacitor; a second period for turning on the switch so that electric charge held in the capacitor in accordance with the sum of the image signal voltage and the threshold voltage is discharged through the transistor; and a third period for supplying a current to the display element through the transistor after the second period.

摘要翻译： 提供一种用于驱动半导体器件的方法，由此可以降低晶体管的阈值电压和迁移率的变化的影响。 半导体器件包括n沟道晶体管，用于控制晶体管的栅极和第一端子之间的电连接的开关，电连接在晶体管的栅极和第二端子之间的电容器和显示元件。 该方法具有用于保持与晶体管的阈值电压对应的电压和电容器中的图像信号电压的和的第一周期; 用于接通开关的第二周期，使得根据图像信号电压和阈值电压的和保持在电容器中的电荷通过晶体管放电; 以及第三周期，用于在第二周期之后通过晶体管向显示元件提供电流。

公开(公告)号：US09035316B2

公开(公告)日：2015-05-19

申请号：US13747503

申请日：2013-01-23

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki

IPC分类号： H01L29/04 ,  H01L27/01 ,  H01L27/088 ,  G02F1/1368 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786 ,  H01L27/12

CPC分类号： H01L27/088 ,  G02F1/1368 ,  H01L21/28114 ,  H01L27/124 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/786 ,  H01L29/78624 ,  H01L29/78627 ,  H01L2029/7863

摘要： A multi-layered gate electrode of a crystalline TFT is constructed as a clad structure formed by deposition of a first gate electrode, a second gate electrode and a third gate electrode, to thereby to enhance the thermal resistance of the gate electrode. Additionally, an n-channel TFT is formed by selective doping to form a low-concentration impunty region which adjoins a channel forming region, and a sub-region overlapped by the gate electrode and a sub-region not overlapped by the gate electrode, to also mitigate a high electric field near the drain of the TFT and to simultaneously prevent the OFF current of the TFT from increasing.

摘要翻译： 构造晶体TFT的多层栅极电极构成为通过沉积第一栅电极，第二栅极电极和第三栅电极而形成的包层结构，从而提高栅电极的热阻。 另外，通过选择性掺杂形成n沟道TFT，以形成与沟道形成区相邻的低浓度势垒区域和与栅电极重叠的子区域和与栅电极不重叠的子区域，形成为 还可以减轻TFT的漏极附近的高电场，同时防止TFT的OFF电流增加。

公开(公告)号：US08957424B2

公开(公告)日：2015-02-17

申请号：US14223366

申请日：2014-03-24

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Koji Ono ,  Hideomi Suzawa ,  Tatsuya Arao

IPC分类号： H01L27/14 ,  H01L33/08 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786 ,  H01L33/62

CPC分类号： H01L27/1222 ,  G02F1/13624 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/127 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L33/08 ,  H01L33/62 ,  H01L2029/7863 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is an electroluminescence device having a substrate, a thin film transistor over the substrate, an insulating film over the thin film transistor, an electroluminescence element over the insulating film, a passivation film over the electroluminescence element, and a counter substrate over the passivation film. The electroluminescence element is configured to emit light through the counter substrate, and a space between the substrate and the counter substrate is filled with a filler. The electroluminescence device is featured by the tapered side surface of a gate electrode of the thin film transistor.

摘要翻译： 公开了一种电致发光器件，其具有衬底，衬底上的薄膜晶体管，薄膜晶体管上的绝缘膜，绝缘膜上的电致发光元件，电致发光元件上的钝化膜以及钝化膜上的对置衬底 。 电致发光元件被配置为通过对置基板发光，并且用填充物填充基板和对向基板之间的空间。 电致发光元件的特征在于薄膜晶体管的栅电极的锥形侧面。