公开(公告)号：US10979042B2

公开(公告)日：2021-04-13

申请号：US16689916

申请日：2019-11-20

Applicant: pSemi Corporation

Inventor： Gary Chunshien Wu

IPC: H03K17/10 ,  H02M3/07 ,  H03K19/0175 ,  H02M3/158 ,  H03K17/687 ,  H03K19/0185 ,  H03K5/003 ,  H03K5/1534 ,  H01L27/12 ,  H01L27/088 ,  H03K5/00 ,  H01L27/092 ,  H02M1/08 ,  H01L21/86 ,  H01L21/84

Abstract: Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion (e.g. DC/DC) and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. According to an aspect, timing control of edges of a control signal to the high voltage semiconductor devices is provided by a basic edge delay circuit that includes a transistor, a current source and a capacitor. An inverter can be selectively coupled, via a switch, to an input and/or an output of the basic edge delay circuit to allow for timing control of a rising edge or a falling edge of the control signal.

公开(公告)号：US10249539B2

公开(公告)日：2019-04-02

申请号：US15846447

申请日：2017-12-19

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  Geng Wang ,  Qintao Zhang

IPC: H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L21/86 ,  H01L21/306 ,  H01L21/3065

Abstract: Embodiments are directed to a method and resulting structures for forming thin and thick gate dielectric nanosheet transistors on the same chip. A first nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on a substrate. A second nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on the substrate. The first nanosheet of the first nanosheet stack is doped and concurrently removed with the first sacrificial layer of the first nanosheet stack and the first sacrificial layer of the second nanosheet stack.

公开(公告)号：US20190006279A1

公开(公告)日：2019-01-03

申请号：US15748608

申请日：2015-08-26

Applicant: Intel Corporation

Inventor： Chen-Guan Lee ,  Vadym Kapinus ,  Pei-Chi Liu ,  Joodong Park ,  Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L23/522 ,  H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L21/86 ,  H01L29/786

CPC classification number: H01L23/5228 ,  H01L21/86 ,  H01L27/0629 ,  H01L28/00 ,  H01L28/22 ,  H01L28/24 ,  H01L29/785 ,  H01L29/78657

Abstract: IC device structures including a lateral compound resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor. Rather than being stacked vertically, a compound resistive trace may include a plurality of resistive materials arranged laterally over a substrate. Along a resistive trace length, a first resistive material is in contact with a sidewall of a second resistive material. A portion of a first resistive material along a centerline of the resistive trace may be replaced with a second resistive material so that the second resistive material is embedded within the first resistive material.

公开(公告)号：US09824885B2

公开(公告)日：2017-11-21

申请号：US15264034

申请日：2016-09-13

Applicant: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration

Inventor： Yeonjoon Park ,  Sang Hyouk Choi

IPC: H01L21/86 ,  H01L21/02 ,  H01L29/267 ,  H01L31/0336 ,  H01L31/12 ,  H01L21/20 ,  H01L21/205 ,  H01L27/15 ,  H01L33/00 ,  H01L31/028 ,  H01L31/0368 ,  H01L31/18 ,  H01L25/16

CPC classification number: H01L21/0242 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02554 ,  H01L21/2011 ,  H01L21/2053 ,  H01L21/2056 ,  H01L25/167 ,  H01L27/15 ,  H01L29/267 ,  H01L31/028 ,  H01L31/0336 ,  H01L31/03682 ,  H01L31/125 ,  H01L31/1804 ,  H01L31/1812 ,  H01L31/1848 ,  H01L31/1852 ,  H01L33/007 ,  H01L2924/0002 ,  Y02E10/544 ,  Y02E10/546 ,  Y02E10/547 ,  Y02P70/521 ,  H01L2924/00

Abstract: One aspect of the present invention is a double sided hybrid crystal structure including a trigonal Sapphire wafer containing a (0001) C-plane and having front and rear sides. The Sapphire wafer is substantially transparent to light in the visible and infrared spectra, and also provides insulation with respect to electromagnetic radio frequency noise. A layer of crystalline Si material having a cubic diamond structure aligned with the cubic direction on the (0001) C-plane and strained as rhombohedron to thereby enable continuous integration of a selected (SiGe) device onto the rear side of the Sapphire wafer. The double sided hybrid crystal structure further includes an integrated III-Nitride crystalline layer on the front side of the Sapphire wafer that enables continuous integration of a selected III-Nitride device on the front side of the Sapphire wafer.

公开(公告)号：US09780728B1

公开(公告)日：2017-10-03

申请号：US15083939

申请日：2016-03-29

Applicant: Peregrine Semiconductor Corporation

Inventor： Daoud Salameh

IPC: H03D7/02 ,  H03D7/14 ,  H03H7/42 ,  H01L23/66 ,  H01L27/06 ,  H01L27/12 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786 ,  H01L21/84 ,  H01L21/86 ,  H01L21/8238

CPC classification number: H03D7/1458 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/86 ,  H01L23/66 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/7838 ,  H01L29/786 ,  H03D7/02 ,  H03D7/1408 ,  H03D7/1441

Abstract: A FET based double balanced mixer (DBM) that exhibits good conversion gain and IIP3 values and provides improved linearity and wide bandwidth. In one embodiment, a first balun is configured to receive a local oscillator (LO) signal and generate two balanced LO signals that are coupled to two corresponding opposing nodes of a four-node FET ring. A second balun is configured to pass an RF signal on the unbalanced side. The FET ring includes at least four FETs connected as branches of a ring, with the source of each FET connected to the drain of a next FET in the ring. Each FET is preferably fabricated as, or configured as, a low threshold voltage device having its gate connected to its drain, which causes the FET to operate as a diode, but with the unique characteristic of having close to a zero turn-on voltage.

公开(公告)号：US09087689B1

公开(公告)日：2015-07-21

申请号：US14329759

申请日：2014-07-11

Applicant: INOSO, LLC

Inventor： Ziep Tran ,  Kiyoshi Mori ,  Giang Trung Dao ,  Michael Edward Ramon

IPC: H01L29/45 ,  H01L29/66 ,  H01L27/02 ,  H01L21/8238 ,  H01L21/82 ,  H01L21/84 ,  H01L21/86 ,  H01L29/20 ,  H01L29/16 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L21/8213 ,  H01L21/8221 ,  H01L21/845 ,  H01L21/86 ,  H01L27/0211 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1211

Abstract: A method of forming a stacked low temperature transistor and related devices. At least some of the illustrative embodiments are methods comprising forming at least one integrated circuit device on a front surface of a bulk semiconductor substrate, and depositing an inter-layer dielectric on the at least one integrated circuit device. A semiconductor layer may then be deposited on the inter-layer dielectric. In some embodiments, a transistor is formed within the semiconductor layer. In some examples, the transistor includes a gate structure formed over the semiconductor layer as well as source/drain regions formed within the semiconductor layer disposed adjacent to and on either side of the gate structure. A metal layer may then be deposited over the transistor, after which an annealing process is performed to induce a reaction between the source/drain regions and the metal layer.

公开(公告)号：US09082817B2

公开(公告)日：2015-07-14

申请号：US14060128

申请日：2013-10-22

Applicant: National Semiconductor Corporation

Inventor： Sandeep R. Bahl ,  Jamal Ramdani

IPC: H01L21/86 ,  H01L21/762 ,  H01L21/02 ,  H01L29/10 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L21/76 ,  H01L29/06 ,  H01L23/485 ,  H01L27/06 ,  H01L27/088

CPC classification number: H01L21/762 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/7605 ,  H01L23/485 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer.

公开(公告)号：US08933453B2

公开(公告)日：2015-01-13

申请号：US13598325

申请日：2012-08-29

Applicant: Youngbae Park ,  Shih Chang Chang ,  Vasudha Gupta ,  John Z. Zhong

Inventor： Youngbae Park ,  Shih Chang Chang ,  Vasudha Gupta ,  John Z. Zhong

IPC: H01L21/86

CPC classification number: G02F1/136286 ,  H01L27/3276

Abstract: Embodiments of the present disclosure related to electronic displays and electronic devices incorporating such displays which employ a device, method, or combination thereof for reducing the width of gate lines and/or data lines in the display. The result of which allows for increased pixel aperture size. The present disclosure provides techniques for reducing the width of gate lines and/or data lines while maintaining an acceptable resistance level in the gate lines and/or data lines.

Abstract translation: 本公开的实施例涉及包含这样的显示器的电子显示器和电子设备，其采用设备，方法或其组合来减少显示器中的栅极线和/或数据线的宽度。 其结果允许增加像素孔径尺寸。 本公开提供了用于在保持栅极线和/或数据线中可接受的电阻水平的同时减小栅极线和/或数据线的宽度的技术。

公开(公告)号：US20130049119A1

公开(公告)日：2013-02-28

申请号：US13339438

申请日：2011-12-29

Applicant: Xiaolu HUANG ,  Gang MAO ,  Yuwen CHEN ,  Xinyun XIE

Inventor： Xiaolu HUANG ,  Gang MAO ,  Yuwen CHEN ,  Xinyun XIE

IPC: H01L27/092 ,  H01L27/12 ,  H01L21/86 ,  H01L21/8238

CPC classification number: H01L21/823857

Abstract: The present invention provides a multi-working voltages CMOS device with single gate oxide layer thickness, gate work functions of CMOS transistors are regulated by implanting ions with different work functions into metal oxide dielectric material layers of the CMOS transistors, thus to realize different flat-band voltages under the condition of single dielectric layer thickness, and realize a multi-working voltages CMOS structure under the condition of single dielectric layer thickness. The present invention overcomes the process complexity of multiple kinds of gate dielectric layer thicknesses needed by traditional multi-working voltages CMOS, simplifies the CMOS process, makes the manufacturing procedure simple and easy to execute, reduces the preparation cost and is suitable for industrial production.

Abstract translation: 本发明提供具有单栅极氧化层厚度的多工作电压CMOS器件，通过将具有不同功函数的离子注入到CMOS晶体管的金属氧化物介电材料层中来调节CMOS晶体管的栅极功能，从而实现不同的平面 - 在单介电层厚度的条件下，实现多层电压CMOS结构，在单介电层厚度条件下实现多工作电压CMOS结构。 本发明克服了传统多工作电压CMOS所需的多种栅极电介质层的工艺复杂性，简化了CMOS工艺，使制造工艺简单易行，降低了制备成本，适合工业生产。

公开(公告)号：US20120252175A1

公开(公告)日：2012-10-04

申请号：US13423716

申请日：2012-03-19

Applicant: Amlan Majumdar ,  XINHUI WANG

Inventor： Amlan Majumdar ,  XINHUI WANG

IPC: H01L21/8238 ,  H01L21/86

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/1203 ,  H01L29/7848

Abstract: A complementary metal-oxide semiconductor (CMOS) structure includes a substrate and a P-type field effect transistor (FET) and an N-type FET disposed adjacent to one another on the substrate. Each FET includes a silicon-on-insulator (SOI) region, a gate electrode disposed on the SOI region, a source stressor, and a drain stressor disposed across from the source stressor relative to the gate electrode, wherein proximities of the source stressor and the drain stressor to a channel of a respective FET are substantially equal.

Abstract translation: 互补金属氧化物半导体（CMOS）结构包括在衬底上彼此相邻布置的衬底和P型场效应晶体管（FET）和N型FET。 每个FET包括绝缘体上硅（SOI）区域，设置在SOI区域上的栅极电极，源极应力源和从源极应力源相对于栅电极相对设置的漏极应力源，其中源极应力源和 相应FET的通道的漏极应力基本相等。