公开(公告)号：US06323554B1

公开(公告)日：2001-11-27

申请号：US09113916

申请日：1998-07-10

Applicant: Rajiv V. Joshi ,  Jerome J. Cuomo ,  Hormazdyar M. Dalal ,  Louis L. Hsu

Inventor： Rajiv V. Joshi ,  Jerome J. Cuomo ,  Hormazdyar M. Dalal ,  Louis L. Hsu

IPC: H01L2348

CPC classification number: H01L21/76843 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76877 ,  H01L23/49866 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10S148/015 ,  Y10S257/915 ,  Y10S438/959 ,  H01L2924/00

Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH4 to WF6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1 mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1 mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

Abstract translation: 用难熔金属覆盖低电阻率金属导体线或通孔允许有效地使用化学机械抛光技术，因为在化学机械抛光期间难熔金属的硬度降低的磨损性质不会划伤，腐蚀或涂抹。 使用低电阻率金属或合金的物理气相沉积（例如，蒸发或准直溅射）以及随后的难熔金属的化学气相沉积（CVD）和随后的平坦化的组合来产生导电线和通孔。 在通过CVD施加难熔金属帽时改变SiH4与WF6的比率允许将钨控制并入钨覆盖层中。 准直溅射允许在电介质中的开口中形成难熔金属衬垫，其适合作为铜基金属化的扩散阻挡层以及CVD钨。 理想地，为了更快地扩散金属如铜，通过两步准直溅射工艺产生衬垫，其中第一层在相对低的真空压力下沉积，其中定向沉积占主导地位（例如，低于1mTorr），并且第二层沉积在较高的 散射沉积占主导地位的真空压力（例如高于1mTorr）。 对于诸如CVD钨的难熔金属，可以在较高的真空压力下使用准直溅射在一个步骤中创建衬垫。

公开(公告)号：US6147402A

公开(公告)日：2000-11-14

申请号：US113918

申请日：1998-07-10

Applicant: Rajiv V. Joshi ,  Jerome J. Cuomo ,  Hormazdyar M. Dalal ,  Louis L. Hsu

Inventor： Rajiv V. Joshi ,  Jerome J. Cuomo ,  Hormazdyar M. Dalal ,  Louis L. Hsu

IPC: H01L21/28 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L29/440 ,  H01L29/460

CPC classification number: H01L21/76843 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76877 ,  H01L23/49866 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10S148/015 ,  Y10S257/915 ,  Y10S438/959

Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH.sub.4 to WF.sub.6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1 mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1 mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

Abstract translation: 用难熔金属覆盖低电阻率金属导体线或通孔允许有效地使用化学机械抛光技术，因为在化学机械抛光期间难熔金属的硬度降低的磨损特性不会划伤，腐蚀或涂抹。 使用低电阻率金属或合金的物理气相沉积（例如，蒸发或准直溅射）以及随后的难熔金属的化学气相沉积（CVD）和随后的平坦化的组合来产生优异的导电线和通孔。 在通过CVD施加难熔金属帽时改变SiH4与WF6的比率允许将钨控制并入钨覆盖层中。 准直溅射允许在电介质中的开口中形成难熔金属衬垫，其适合作为铜基金属化的扩散阻挡层以及CVD钨。 理想地，为了更快地扩散金属如铜，通过两步准直溅射工艺产生衬垫，其中第一层在相对低的真空压力下沉积，其中定向沉积占主导地位（例如，低于1mTorr），并且第二层沉积在较高的 散射沉积占主导地位的真空压力（例如高于1mTorr）。 对于诸如CVD钨的难熔金属，可以在较高的真空压力下使用准直溅射在一个步骤中创建衬垫。

公开(公告)号：US5976975A

公开(公告)日：1999-11-02

申请号：US113917

申请日：1998-07-10

Applicant: Rajiv V. Joshi ,  Jerome J. Cuomo ,  Hormazdyar M. Dalal ,  Louis L. Hsu

Inventor： Rajiv V. Joshi ,  Jerome J. Cuomo ,  Hormazdyar M. Dalal ,  Louis L. Hsu

IPC: H01L21/28 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44

CPC classification number: H01L21/76843 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76877 ,  H01L23/49866 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10S148/015 ,  Y10S257/915 ,  Y10S438/959

Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the-hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH.sub.4 to WF.sub.6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below lmtorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1 mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

Abstract translation: 用难熔金属覆盖低电阻率金属导体线或通孔允许有效地使用化学机械抛光技术，因为在化学机械抛光期间难熔金属的硬度降低的磨损特性不会划伤，腐蚀或涂抹。 使用低电阻率金属或合金的物理气相沉积（例如，蒸发或准直溅射）以及随后的难熔金属的化学气相沉积（CVD）和随后的平坦化的组合来产生优异的导电线和通孔。 在通过CVD施加难熔金属帽时改变SiH4与WF6的比率允许将钨控制并入钨覆盖层中。 准直溅射允许在电介质中的开口中形成难熔金属衬垫，其适合作为铜基金属化的扩散阻挡层以及CVD钨。 理想地，为了更快地扩散金属如铜，通过两步准直溅射工艺产生衬垫，其中第一层在相对低的真空压力下沉积，其中定向沉积占主导地位（例如，低于1mtorr），并且在较高真空下沉积第二层 散射沉积占主导地位的压力（例如高于1mTorr）。 对于诸如CVD钨的难熔金属，可以在较高的真空压力下使用准直溅射在一个步骤中创建衬垫。

公开(公告)号：US5519254A

公开(公告)日：1996-05-21

申请号：US289310

申请日：1994-08-11

Applicant: Suguru Tabara

Inventor： Suguru Tabara

IPC: H01L21/302 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L29/43 ,  H01L21/265 ,  H01L21/283

CPC classification number: H01L21/76838 ,  Y10S148/015

Abstract: A lower wiring layer is formed on an insulating film 12 covering a semiconductor substrate 10. The wiring layer 14 has a laminated structure of a barrier metal layer such as WSi2, an Al or Al alloy layer, and a cap metal layer such as WSi.sub.2 formed in this order from the bottom. The cap metal layer is caused to contain conductive material such as Al by using an ion injection method or the like. After forming an insulating film covering the wiring layer, a contact hole is formed in the insulating film by a dry etching process using a resist layer as a mask. The dry etching process uses a fluorine based gas such as CHF.sub.3 as the etching gas. With this etching gas, fluoride such as Al fluoride (AlF.sub.3) is generated to suppress the etching of the cap metal layer.

Abstract translation: 在覆盖半导体衬底10的绝缘膜12上形成下布线层。布线层14具有阻挡金属层如WSi2，Al或Al合金层和诸如WSi2的帽金属层的叠层结构 从这个顺序从底部。 通过使用离子注入法等使帽金属层含有诸如Al的导电材料。 在形成覆盖布线层的绝缘膜之后，通过使用抗蚀剂层作为掩模的干蚀刻工艺在绝缘膜中形成接触孔。 干蚀刻工艺使用诸如CHF 3的氟基气体作为蚀刻气体。 利用这种蚀刻气体，产生氟化物如AlF 3（AlF 3）以抑制帽金属层的蚀刻。

公开(公告)号：US5447875A

公开(公告)日：1995-09-05

申请号：US240799

申请日：1994-05-11

Applicant: Mehrdad Moslehi

Inventor： Mehrdad Moslehi

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/78 ,  H01L21/283

CPC classification number: H01L29/66507 ,  H01L29/66545 ,  Y10S148/015 ,  Y10S148/019

Abstract: A method of forming a self-aligned silicided gate (44) in a semiconductor device (10). A gate electrode having a conductive body (22) and a disposable cap (24) is formed on the surface of the semiconductor body. A sidewall spacer (32) is formed on the sidewall edges of the gate electrode. A surface dielectric (36) is formed over the exposed semiconductor surface adjacent the sidewall spacers (32) and field insulating layer (18). The disposable cap (24) prevents dielectric formation over gate electrode (22). Source/drain junction regions (34) are formed by ion implantation or another suitable doping method in the surface of the semiconductor body adjacent the gate electrode. The disposable cap (24) is then selectively removed and a silicide layer (40) is formed over the gate electrode using a self-aligned silicide react process. An optional additional self-aligned silicide process may be used to form a source/drain junction silicide layer which is thinner than the gate silicide layer (40).

Abstract translation: 一种在半导体器件（10）中形成自对准硅化物栅极（44）的方法。 在半导体本体的表面上形成具有导电体（22）和一次性盖（24）的栅电极。 侧壁间隔件（32）形成在栅电极的侧壁边缘上。 在邻近侧壁间隔物（32）和场绝缘层（18）的暴露的半导体表面之上形成表面电介质（36）。 一次性盖（24）防止在栅电极（22）上形成电介质。 源极/漏极结区域（34）通过离子注入或其它合适的掺杂方法形成在与栅电极相邻的半导体本体的表面中。 然后选择性地去除一次性盖（24），并且使用自对准硅化物反应工艺在栅电极上形成硅化物层（40）。 可以使用可选的另外的自对准硅化物工艺来形成比栅极硅化物层（40）薄的源极/漏极结硅化物层。

公开(公告)号：US5443996A

公开(公告)日：1995-08-22

申请号：US522775

申请日：1990-05-14

Applicant: Steven S. Lee ,  Kenneth P. Fuchs ,  Gayle W. Miller

Inventor： Steven S. Lee ,  Kenneth P. Fuchs ,  Gayle W. Miller

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/336 ,  H01L21/768 ,  H01L23/52 ,  H01L29/78 ,  H01L21/44

CPC classification number: H01L21/76895 ,  H01L2924/0002 ,  Y10S148/015 ,  Y10S148/019 ,  Y10S148/147

Abstract: A process for forming a titanium silicide local interconnect between electrodes separated by a dielectric insulator on an integrated circuit. A first layer of titanium is formed on the insulator, and a layer of silicon is formed on the titanium. The silicon layer is masked and etched to form a silicon strip connecting the electrodes, and an overlying second layer of titanium is formed over the silicon strip. The titanium and silicon are heated to form nonsilicidized titanium over a strip of titanium silicide, and the nonsilicidized titanium is removed.

Abstract translation: 一种用于在由集成电路上的介质绝缘体隔开的电极之间形成钛硅化物局部互连的工艺。 在绝缘体上形成第一层钛，在钛上形成一层硅。 掩模和蚀刻硅层以形成连接电极的硅带，并且在硅带上形成覆盖的第二层钛。 钛和硅被加热以在硅化钛条上形成非硅化钛，并除去非硅化的钛。

公开(公告)号：US5403779A

公开(公告)日：1995-04-04

申请号：US928335

申请日：1992-08-12

Applicant: Rajiv V. Joshi ,  Jerome J. Cuomo ,  Hormazdyar M. Dalal ,  Louis L. Hsu

Inventor： Rajiv V. Joshi ,  Jerome J. Cuomo ,  Hormazdyar M. Dalal ,  Louis L. Hsu

IPC: H01L21/28 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44 ,  H01L21/48

CPC classification number: H01L21/76843 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76877 ,  H01L23/49866 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10S148/015 ,  Y10S257/915 ,  Y10S438/959

Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH.sub.4 to WF.sub.6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1 mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1 mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

Abstract translation: 用难熔金属覆盖低电阻率金属导体线或通孔允许有效地使用化学机械抛光技术，因为在化学机械抛光期间难熔金属的硬度降低的磨损性质不会划伤，腐蚀或涂抹。 使用低电阻率金属或合金的物理气相沉积（例如，蒸发或准直溅射）以及随后的难熔金属的化学气相沉积（CVD）和随后的平坦化的组合来产生优异的导电线和通孔。 在通过CVD施加难熔金属帽时改变SiH4与WF6的比率允许将钨控制并入钨覆盖层中。 准直溅射允许在电介质中的开口中形成难熔金属衬垫，其适合作为铜基金属化的扩散阻挡层以及CVD钨。 理想地，为了更快地扩散金属如铜，通过两步准直溅射工艺产生衬垫，其中第一层在相对低的真空压力下沉积，其中定向沉积占主导地位（例如，低于1mTorr），并且第二层沉积在较高的 散射沉积占主导地位的真空压力（例如高于1mTorr）。 对于诸如CVD钨的难熔金属，可以在较高的真空压力下使用准直溅射在一个步骤中创建衬垫。

公开(公告)号：US5399527A

公开(公告)日：1995-03-21

申请号：US36673

申请日：1993-03-25

Applicant: Suguru Tabara

Inventor： Suguru Tabara

IPC: H01L21/302 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L29/43 ,  H01L21/265 ,  H01L21/283

CPC classification number: H01L21/76838 ,  Y10S148/015

Abstract: A lower wiring layer is formed on an insulating film 12 covering a semiconductor substrate 10. The wiring layer 14 has a laminated structure of a barrier metal layer such as Wsi.sub.2, an Al or Al alloy layer, and a cap metal layer such as WSi.sub.2 formed in this order from the bottom. The cap metal layer is caused to contain conductive material such as Al by using an ion injection method or the like. After forming an insulating film covering the wiring layer, a contact hole is formed in the insulating film by a dry etching process using a resist layer as a mask. The dry etching process uses a fluorine based gas such as CHF.sub.3 as the etching gas. With this etching gas, fluoride such as Al fluoride (AlF.sub.3) is generated to suppress the etching of the cap metal layer.

Abstract translation: 在覆盖半导体衬底10的绝缘膜12上形成下布线层。布线层14具有诸如Wsi2，Al或Al合金层的阻挡金属层和形成WSi2的帽金属层的叠层结构 从这个顺序从底部。 通过使用离子注入法等使帽金属层含有诸如Al的导电材料。 在形成覆盖布线层的绝缘膜之后，通过使用抗蚀剂层作为掩模的干蚀刻工艺在绝缘膜中形成接触孔。 干蚀刻工艺使用诸如CHF 3的氟基气体作为蚀刻气体。 利用该蚀刻气体，产生氟化物（AlF 3）等氟化物以抑制帽金属层的蚀刻。

公开(公告)号：US5366928A

公开(公告)日：1994-11-22

申请号：US73244

申请日：1993-06-04

Applicant: Robertus A. M. Wolters ,  Alexander G. M. Jonkers

Inventor： Robertus A. M. Wolters ,  Alexander G. M. Jonkers

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L23/31 ,  H01L29/78 ,  H01L21/283

CPC classification number: H01L23/3157 ,  H01L21/28518 ,  H01L21/76895 ,  H01L2924/0002 ,  Y10S148/015 ,  Y10S438/902

Abstract: A method of manufacturing a semiconductor device is set forth comprising a semiconductor body (1) having a surface (2) adjoined by a semiconductor region (3) and a field oxide region (4) surrounding this region, on which surface (2) is provided a metal layer (13), in which a conductor track (17, 18) is formed, after which an isolating layer of silicon oxide (19) is deposited over the conductor track (17, 18) on the surface (2). According to the invention, before the layer of silicon oxide (19) is provided over the conductor track (17, 18), this track is provided with a top layer (16) of an oxidation-preventing material. By providing this top layer (16), it is avoided that the conductor track (17, 18) covered by silicon oxide (19) has a high electrical resistance or even an electrical interruption.

Abstract translation: 提出了一种制造半导体器件的方法，其包括具有邻接半导体区域（3）的表面（2）和围绕该区域的场氧化物区域（4）的半导体本体（1），表面（2） 提供了形成导体轨道（17,18）的金属层（13），之后在表面（2）上的导体轨道（17,18）上沉积氧化硅隔离层（19）。 根据本发明，在氧化硅层（19）设置在导体轨道（17,18）之上之前，该轨道设置有防氧化材料的顶层（16）。 通过设置该顶层（16），避免被氧化硅（19）覆盖的导体轨道（17,18）具有高电阻或甚至电中断。

公开(公告)号：US5256550A

公开(公告)日：1993-10-26

申请号：US715054

申请日：1991-06-12

Applicant: Stephen Laderman ,  Martin Scott ,  Theodore I. Kamins ,  Judy L. Hoyt ,  Clifford A. King ,  James F. Gibbons ,  David B. Noble

Inventor： Stephen Laderman ,  Martin Scott ,  Theodore I. Kamins ,  Judy L. Hoyt ,  Clifford A. King ,  James F. Gibbons ,  David B. Noble

IPC: H01L21/20 ,  H01L21/205

CPC classification number: H01L21/0262 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02631 ,  Y10S148/015 ,  Y10S438/902 ,  Y10S438/938

Abstract: The present invention comprises a method of fabricating devices and circuits employing at least one heteroepitaxial layer under strain. The thickness of the heteroepitaxial layer is more than two times the calculated equilibrium critical thickness for an uncapped heteroepitaxial layer upon a crystalline substrate, based on previously known equilibrium theory for the uncapped layer. Subsequent to growth of the heteroepitaxial layer, the structure is processed at temperatures higher than the growth temperature of the heteroepitaxial layer.The strained heteroepitaxial layer (second layer) is epitaxially grown upon the surface of a first, underlaying crystalline layer, creating a heterojunction. Subsequently a third crystalline layer is deposited or grown upon the major exposed surface of the second, strained heteroepitaxial layer. The preferred manner of growth of the third crystalline layer is epitaxial growth. The composition of the third crystalline layer must be such that upon deposition or growth, the third layer substantially continuously binds to the heteroepitaxial structure of the second layer. Subsequent to growth of the at least three layer structure, the structure is processed at temperatures in excess of the growth temperature of the second heteroepitaxial layer. Presence of the third crystalline layer prevents the generation of a substantial amount of misfit dislocations between the first crystalline layer substrate and the second heteroepitaxial layer.

Abstract translation: 本发明包括一种在应变下使用至少一个异质外延层的器件和电路的制造方法。 基于先前已知的无盖层的平衡理论，异质外延层的厚度超过了在结晶衬底上的无盖异质外延层的计算的平衡临界厚度的两倍。 在异质外延层的生长之后，在高于异质外延层的生长温度的温度下处理该结构。 应变异质外延层（第二层）在第一底层晶体层的表面上外延生长，产生异质结。 随后，在第二应变异质外延层的主要暴露表面上沉积或生长第三晶体层。 第三晶体层的优选生长方式是外延生长。 第三结晶层的组成必须使得在沉积或生长时，第三层基本上连续地结合到第二层的异质外延结构。 在至少三层结构生长之后，在超过第二异质外延层的生长温度的温度下处理该结构。 第三结晶层的存在防止在第一晶体层衬底和第二异质外延层之间产生大量的失配位错。