公开(公告)号：US20120188002A1

公开(公告)日：2012-07-26

申请号：US13438230

申请日：2012-04-03

Applicant: Louis L. Hsu ,  Xu Ouyang ,  Chih-Chao Yang

Inventor： Louis L. Hsu ,  Xu Ouyang ,  Chih-Chao Yang

IPC: H03K17/687 ,  H01L21/02

CPC classification number: H01L28/40 ,  H01L22/14 ,  H01L22/22 ,  H01L22/34 ,  H01L23/5223 ,  H01L27/0688 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  Y10T307/865 ,  H01L2924/00

Abstract: A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.

Abstract translation: 模块化电容器阵列包括多个电容器模块。 每个电容器模块包括电容器和被配置为电气断开电容器的开关装置。 开关装置包括：感测单元，被配置为检测电容器的泄漏电平，使得如果泄漏电流超过预定电平，则开关装置电连接电容器。 每个电容器模块可以包括单个电容器板，两个电容器板或多于两个的电容器板。 泄漏传感器和开关装置用于电气断开任何电容器阵列的电容器模块，从而保护电容器阵列免于漏电。

公开(公告)号：US08198174B2

公开(公告)日：2012-06-12

申请号：US12536176

申请日：2009-08-05

Applicant: Louis L. Hsu ,  Brian L. Ji ,  Fei Liu ,  Conal E. Murray

Inventor： Louis L. Hsu ,  Brian L. Ji ,  Fei Liu ,  Conal E. Murray

IPC: H01L21/44

CPC classification number: H01L23/467 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional (3D) chip stack structure and method of fabricating the structure thereof are provided. The 3D chip stack structure includes a plurality of vertically stacked chips which are interconnected and bonded together, wherein each of the vertically stacked chips include one or more IC device strata. The 3D chip stack structure further includes an air channel interconnect network embedded within the chip stack structure, and wherein the air channel interconnect network is formed in between at least two wafers bonded to each other of the vertically stacked wafers and in between at least two bonded wafers of the vertically stacked wafers at a bonding interface thereof. In addition, the 3D chip stack structure further includes one or more openings in a peripheral region of the chip stack structure that lead into and out of the air channel interconnect network, so that air can flow into and out of the air channel interconnect network through the one or more openings to remove heat from the chip stack structure.

Abstract translation: 提供三维（3D）芯片堆叠结构及其结构的制造方法。 3D芯片堆叠结构包括互连并结合在一起的多个垂直堆叠的芯片，其中每个垂直堆叠的芯片包括一个或多个IC器件层。 3D芯片堆叠结构还包括嵌入在芯片堆叠结构内的空气通道互连网络，并且其中空气通道互连网络形成在至少两个晶片之间，所述至少两个晶片彼此接合在垂直堆叠的晶片之间，并且在至少两个结合 在其接合界面处的垂直堆叠的晶片的晶片。 此外，3D芯片堆叠结构还包括在芯片堆叠结构的外围区域中的一个或多个开口，其引入和流出空气通道互连网络，使得空气可以流入和流出空气通道互连网络，通过 一个或多个开口以从芯片堆叠结构移除热量。

公开(公告)号：US20110254121A1

公开(公告)日：2011-10-20

申请号：US12761780

申请日：2010-04-16

Applicant: Kangguo Cheng ,  Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

Inventor： Kangguo Cheng ,  Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

IPC: H01L23/525 ,  H01L21/768 ,  G06F17/50

CPC classification number: H01L23/5252 ,  G06F17/505 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features.

Abstract translation: 提供了电压可编程的抗熔丝结构和方法，其包括位于介于两个相邻导电特征之间的电介质表面上的至少一个导电材料岛。 在一个实施例中，反熔丝结构包括具有嵌入其中的至少两个相邻导电特征的电介质材料。 至少一个导电材料岛位于介电材料的位于至少两个相邻导电特征之间的上表面上。 电介质覆盖层位于电介质材料的暴露表面上，至少一个导电材料岛和至少两个相邻的导电特征。 当反熔丝结构处于编程状态时，介电击穿路径存在于介电材料中，介电材料位于至少一个导电材料岛之下，该导电材料岛传导电流以电耦合两个相邻导电特征。

公开(公告)号：US07994042B2

公开(公告)日：2011-08-09

申请号：US11924735

申请日：2007-10-26

Applicant: Louis L. Hsu ,  Rajiv V. Joshi ,  David W. Kruger

Inventor： Louis L. Hsu ,  Rajiv V. Joshi ,  David W. Kruger

IPC: H01L21/00

CPC classification number: H01L21/76816 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/573 ,  H01L27/02 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer.

Abstract translation: 提供了反逆向工程技术。 一方面，提供了一种在绝缘层中形成至少一个特征的方法。 该方法包括以下步骤。 离子选择性地植入绝缘层中，以在绝缘层内形成至少一个注入区域，所述注入离子被配置为改变通过植入区域内的绝缘层的蚀刻速率。 蚀刻绝缘层，同时在植入区域内和植入区域外部形成至少一个空隙，其中通过绝缘层在植入区域内的蚀刻速率与通过绝缘体的蚀刻速率不同 在植入区域外侧。 空隙填充有至少一种导体材料以在绝缘层中形成特征。

公开(公告)号：US20110069425A1

公开(公告)日：2011-03-24

申请号：US12565802

申请日：2009-09-24

Applicant: Louis L. Hsu ,  Xu Ouyang ,  Chih-Chao Yang

Inventor： Louis L. Hsu ,  Xu Ouyang ,  Chih-Chao Yang

IPC: H01G4/38 ,  H01L21/02 ,  H03K17/687

CPC classification number: H01L28/40 ,  H01L22/14 ,  H01L22/22 ,  H01L22/34 ,  H01L23/5223 ,  H01L27/0688 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  Y10T307/865 ,  H01L2924/00

Abstract: A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.

Abstract translation: 模块化电容器阵列包括多个电容器模块。 每个电容器模块包括电容器和被配置为电气断开电容器的开关装置。 开关装置包括：感测单元，被配置为检测电容器的泄漏电平，使得如果泄漏电流超过预定电平，则开关装置电连接电容器。 每个电容器模块可以包括单个电容器板，两个电容器板或多于两个的电容器板。 泄漏传感器和开关装置用于电气断开任何电容器阵列的电容器模块，从而保护电容器阵列免于漏电。

公开(公告)号：US07855563B2

公开(公告)日：2010-12-21

申请号：US11766268

申请日：2007-06-21

Applicant: Huihao Xu ,  Louis L. Hsu ,  Kevin G. Kramer ,  James D. Rockrohr ,  Michael A. Sorna

Inventor： Huihao Xu ,  Louis L. Hsu ,  Kevin G. Kramer ,  James D. Rockrohr ,  Michael A. Sorna

IPC: G01R31/00 ,  H04B3/46

CPC classification number: G01R31/041 ,  G01R31/026

Abstract: A system is provided for detecting a fault in a signal transmission path. In one embodiment, the system can include a variable amplitude signal attenuator which is operable to modify an input signal by variably attenuating a signal voltage swing of the input signal. Desirably, the input signal is attenuated only when transitioning from a high signal voltage level towards a low signal voltage level d variably, such that a larger high-to-low signal voltage swing is attenuated more than a smaller high-to-low signal voltage swing. Desirably, a comparator, which may apply hysteresis to the output signals, may detect a crossing of a reference voltage level by the modified input signal. In this way, when the comparator does not detect an expected crossing of the reference voltage level by the modified input signal, a determination can be made that a fault exists in the signal transmission path.

Abstract translation: 提供了一种用于检测信号传输路径中的故障的系统。 在一个实施例中，系统可以包括可变幅度信号衰减器，其可操作以通过可变地衰减输入信号的信号电压摆幅来修改输入信号。 期望地，只有当从高信号电压电平转换到低信号电压电平d时，输入信号才被衰减，使得较高的高电平到低的信号电压摆幅比较小的高到低信号电压衰减 摇摆。 期望地，可能对输出信号施加迟滞的比较器可以检测参考电压电平与修改的输入信号的交叉。 以这种方式，当比较器没有检测到通过修改的输入信号的参考电压电平的预期交叉时，可以确定在信号传输路径中存在故障。

公开(公告)号：US07804148B2

公开(公告)日：2010-09-28

申请号：US11355799

申请日：2006-02-16

Applicant: Louis L. Hsu ,  Jack A. Mandelman ,  Chandrasekhar Narayan ,  Chun-Yung Sung

Inventor： Louis L. Hsu ,  Jack A. Mandelman ,  Chandrasekhar Narayan ,  Chun-Yung Sung

IPC: H01L23/58 ,  H01L31/058 ,  H01L31/02 ,  H01L31/0232 ,  H01L31/024 ,  H01L21/033 ,  H01L21/00

CPC classification number: H01L21/268 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An opto-thermal annealing mask stack layer includes a thermal dissipative layer located over a substrate. A reflective layer is located upon the thermal dissipative layer. A transparent capping layer, that may have a thickness from about 10 to about 100 angstroms, is located upon the reflective layer. The opto-thermal annealing mask layer may be used as a gate electrode within a field effect device.

Abstract translation: 光热退火掩模层叠层包括位于衬底上的散热层。 反射层位于热耗散层上。 可以具有约10至约100埃厚度的透明覆盖层位于反射层上。 光热退火掩模层可以用作场效应器件中的栅电极。

公开(公告)号：US07774660B2

公开(公告)日：2010-08-10

申请号：US12131307

申请日：2008-06-02

Applicant: Louis L. Hsu ,  Gregory J. Fredeman ,  Rajiv V. Joshi ,  Toshiaki Kirihata

Inventor： Louis L. Hsu ,  Gregory J. Fredeman ,  Rajiv V. Joshi ,  Toshiaki Kirihata

IPC: G11C29/00

CPC classification number: G11C29/808

Abstract: A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.

Abstract translation: 提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。 行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 其中所述复制逻辑模块被编程为根据可选择的修复字段大小将所述至少一个故障地址复制到对应于预定数量的存储体的行熔丝阵列中的行熔丝信息。

公开(公告)号：US07719135B2

公开(公告)日：2010-05-18

申请号：US12145622

申请日：2008-06-25

Applicant: Rajiv V Joshi ,  Louis L Hsu

Inventor： Rajiv V Joshi ,  Louis L Hsu

IPC: H02J1/10

CPC classification number: G11C11/4074 ,  G06F1/26 ,  G11C5/14 ,  Y10T307/305

Abstract: There is provided a circuit for managing a multi-level power supply. The circuit includes a comparator that compares a voltage level (Vs1) of a lower voltage supply bus to a voltage level (Vs2) of a higher voltage supply bus, and a switch that routes current from the lower voltage supply bus to the higher voltage supply bus if Vs2

Abstract translation: 提供了一种用于管理多电平电源的电路。 电路包括比较器，其将较低电压供应总线的电压电平（Vs1）与较高电压电源总线的电压电平（Vs2）进行比较，以及将电流从低电压供应总线传送到较高电压源的开关 总线如果Vs2

公开(公告)号：US20090212341A1

公开(公告)日：2009-08-27

申请号：US12034899

申请日：2008-02-21

Applicant: Kangguo Cheng ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis L. Hsu ,  Jack A. Mandelman

Inventor： Kangguo Cheng ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis L. Hsu ,  Jack A. Mandelman

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L29/66795 ,  H01L29/7841 ,  H01L29/7853

Abstract: An epitaxial semiconductor layer or a stack of a silicon germanium alloy layer and an epitaxial strained silicon layer is formed on outer sidewalls of a porous silicon portion on a substrate. The porous silicon portion and any silicon germanium alloy material are removed and a semitubular epitaxial semiconductor structure in a three-walled configuration is formed. A semitubular field effect transistor comprising inner and outer gate dielectric layers, an inner gate electrode, an outer gate electrode, and source and drain regions is formed on the semitubular epitaxial semiconductor structure. The semitubular field effect transistor may operate as an SOI transistor with a tighter channel control through the inner and outer gate electrodes, or as a memory device storing electrical charges in the body region within the semitubular epitaxial semiconductor structure.

Abstract translation: 在衬底上的多孔硅部分的外侧壁上形成硅锗合金层和外延应变硅层的外延半导体层或叠层。 去除多孔硅部分和任何硅锗合金材料，并形成三壁结构的半管状外延半导体结构。 在半管外延半导体结构上形成包括内栅电介质层和外栅电介质层，内栅电极，外栅电极以及源极和漏极区的半管场效应晶体管。 半管场效应晶体管可以作为具有通过内部和外部栅极电极的更严格的沟道控制的SOI晶体管，或作为在半管外延半导体结构内的体区中存储电荷的存储器件。