公开(公告)号：US5068704A

公开(公告)日：1991-11-26

申请号：US520446

申请日：1990-05-08

Applicant: Akio Nakagawa ,  Kaoru Imamura ,  Ryo Sato ,  Tadahide Hoshi

Inventor： Akio Nakagawa ,  Kaoru Imamura ,  Ryo Sato ,  Tadahide Hoshi

IPC: H01L29/68 ,  H01L21/02 ,  H01L21/18 ,  H01L21/22 ,  H01L21/331 ,  H01L21/336 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/66333 ,  H01L21/187 ,  H01L21/2205 ,  Y10S148/012 ,  Y10S148/157

Abstract: A method of manufacturing a semiconductor device comprising the steps of bringing a mirror-polished surface of a first semiconductor substrate of a first conductivity type into contact with a mirror-polished surface of a second semiconductor substrate of a second conductivity type having an impurity concentration which is lower than that of said first conductivity type, in a clean atmosphere, and thermally heating said first and second semiconductor substrates so that they unite. Impurity is diffused from said first semiconductor substrate into said second semiconductor substrate, thereby forming a diffusion layer of a first conductivity type in said second semiconductor substrate. A total amount of impurity of said diffusion layer is 1.times.10.sup.13 /cm.sup.2 to 2.times.10.sup.15 /cm.sup.2, to form a pn junction in said second semiconductor substrate.

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：将具有第一导电类型的第一半导体衬底的镜面抛光表面与具有杂质浓度的第二导电类型的第二半导体衬底的镜面抛光表面接触， 在清洁的气氛中低于所述第一导电类型，并且热加热所述第一和第二半导体衬底以使它们团结起来。 杂质从所述第一半导体衬底扩散到所述第二半导体衬底中，从而在所述第二半导体衬底中形成第一导电类型的扩散层。 所述扩散层的杂质的总量为1×10 13 / cm 2至2×10 15 / cm 2，以在所述第二半导体衬底中形成pn结。

公开(公告)号：US3607468A

公开(公告)日：1971-09-21

申请号：US3607468D

申请日：1968-10-07

Applicant: IBM

Inventor： CHANG JOSEPH J F ,  VORA MADHUKAR B

IPC: A47L15/42 ,  G01D5/244 ,  H01L21/00 ,  H01L21/22 ,  H01L21/265 ,  H01L21/331 ,  H01L27/00 ,  H01L29/36 ,  H01L29/73 ,  H01L7/44

CPC classification number: H01L29/36 ,  A47L15/42 ,  G01D5/244 ,  H01L21/00 ,  H01L21/22 ,  H01L21/265 ,  H01L27/00 ,  H01L29/73 ,  Y10S148/037 ,  Y10S148/04 ,  Y10S148/085 ,  Y10S148/151 ,  Y10S148/157

Abstract: A method for making a high-performance NPN silicon semiconductor device which has an arsenic emitter which gives a substantial improvement in transistor speed and current gain over similar phosphorous emitters. Arsenic atoms in the emitter region tend to squeeze the P-type impurity, such as boron in the base into a narrow base layer. For the same integrated base doping, a much narrower base can be obtained with arsenic-doped emitters than with phosphorous-doped emitters.

公开(公告)号：US3454434A

公开(公告)日：1969-07-08

申请号：US3454434D

申请日：1966-05-09

Applicant: MOTOROLA INC

Inventor： JACKSON DON M JR ,  FRAZEE ORVILLE PHILLIP ,  WALDOW PETER

IPC: H01L21/205 ,  H01L29/00 ,  H01L29/06 ,  H01L29/86 ,  H01L3/14 ,  H01L7/36 ,  H01L9/12

CPC classification number: H01L29/06 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/00 ,  H01L29/86 ,  Y10S148/025 ,  Y10S148/157

公开(公告)号：US5397730A

公开(公告)日：1995-03-14

申请号：US98653

申请日：1993-07-15

Applicant: Junichi Hojo ,  Toshiaki Wakayama

Inventor： Junichi Hojo ,  Toshiaki Wakayama

IPC: H01L27/148 ,  H04N5/335 ,  H04N5/341 ,  H04N5/359 ,  H04N5/3728 ,  H01L21/74

CPC classification number: H01L27/14831 ,  Y10S148/157

Abstract: In a horizontal transfer section of a solid state imager, a horizontal transfer efficiency can be improved while other element sections are prevented from being substantially affected. In a solid state imager having a horizontal transfer section comprised of a well-region of a second conductivity type formed on the surface of a semiconductor substrate of a first conductivity type and a signal charge transfer region formed on the surface of the well-region of the second conductivity type, the well-region is formed completely in a depletion state by the implantation of impurities into this well-region. The horizontal transfer efficiency is thus improved.

Abstract translation: 在固态成像器的水平转印部分中，可以提高水平转印效率，同时防止其他元件部分受到显着影响。 在具有由在第一导电类型的半导体衬底的表面上形成的第二导电类型的阱区和形成在阱区的表面上的信号电荷转移区组成的水平转移区的固态成像器中， 第二导电类型，通过将杂质注入该阱区，阱区完全形成为耗尽状态。 从而提高了水平传送效率。

公开(公告)号：US4883769A

公开(公告)日：1989-11-28

申请号：US234089

申请日：1988-08-18

Applicant: Thomas R. Au Coin ,  Walter D. Braddock IV ,  Gerald J. Iafrate

Inventor： Thomas R. Au Coin ,  Walter D. Braddock IV ,  Gerald J. Iafrate

IPC: H01L21/027 ,  H01L21/8252 ,  H01L29/12 ,  H01L21/20 ,  H01L21/225

CPC classification number: B82Y10/00 ,  H01L21/0273 ,  H01L21/8252 ,  H01L29/127 ,  Y10S148/003 ,  Y10S148/015 ,  Y10S148/157 ,  Y10S438/916

Abstract: Multidimensional quantum-well arrays are made by electron-beam lithographicatterning, followed by solid-state diffusion.

Abstract translation: 多维量子阱阵列通过电子束光刻图案化，随后进行固态扩散。

公开(公告)号：US4049478A

公开(公告)日：1977-09-20

申请号：US638496

申请日：1975-12-08

Applicant: Hitendra N. Ghosh ,  Madhukar L. Joshi ,  Tsu-Hsing Yeh

Inventor： Hitendra N. Ghosh ,  Madhukar L. Joshi ,  Tsu-Hsing Yeh

IPC: H01L21/22 ,  H01L21/223 ,  H01L29/08 ,  H01L21/20

CPC classification number: H01L21/22 ,  H01L21/223 ,  H01L29/0804 ,  Y10S148/04 ,  Y10S148/041 ,  Y10S148/085 ,  Y10S148/157

Abstract: A substantially square N-type impurity distribution profile in a silicon substrate produces much superior dc and ac characteristics in PN junction devices than can be expected from the usual phosphorus distribution profile. Such a square profile is obtained by diffusion of arsenic in the silicon substrate. The sharper impurity gradient allows a relatively low surface concentration to be used for the device. This lower surface concentration relieves precipitation and dislocation problems.

Abstract translation: 在硅衬底中基本上为方形的N型杂质分布曲线在PN结器件中产生比从通常的磷分布曲线预期的更好的直流和交流特性。 通过砷在硅衬底中的扩散来获得这样的正方形。 更尖锐的杂质梯度允许相对低的表面浓度用于器件。 这种较低的表面浓度可以减轻沉淀和脱位问题。

公开(公告)号：US3777227A

公开(公告)日：1973-12-04

申请号：US3777227D

申请日：1972-08-21

Applicant: WESTINGHOUSE ELECTRIC CORP

Inventor： KRISHNA S ,  DAVIS J

IPC: H01L21/00 ,  H01L21/331 ,  H01L29/00 ,  H01L29/73 ,  H01L5/00

CPC classification number: H01L29/00 ,  H01L21/00 ,  H01L29/73 ,  Y10S148/04 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/121 ,  Y10S148/135 ,  Y10S148/151 ,  Y10S148/157

Abstract: An NPN transistor with high voltage and high current capacities is provided in a semiconductor body having a thin internal portion and a thick integral peripheral portion. The thin portion has a substantially uniform width of greater than about 28 microns and oppositely facing surface areas each of greater than about 0.10 cm2. The thick peripheral portion has a width greater than about 150 microns and annular dimension i.e. radial width greater than 10 microns. The base region has two contiguous impurity portions. A first impurity portion adjoins a major, preferably planar surface of the semiconductor body at the peripheral portion and has an impurity concentration of boron of at least 1 X 1019 atoms per cubic centimeter at the surface and a steep impurity concentration gradient to provide good ohmic and thermal properties. A second contiguous impurity portion is in internal portions of the body between emitter and collector regions and has a lower impurity concentration of gallium and/or aluminum and shallower impurity concentration gradient than the first impurity portion. Preferably, first and second impurity portions of the base region are formed by the simultaneous diffusion of boron and gallium and/or aluminum.

Abstract translation: 具有高电压和高电流容量的NPN晶体管设置在具有薄的内部部分和厚整体的周边部分的半导体本体中。 薄部分具有大于约28微米的基本均匀的宽度，并且相对面对的表面区域大于约0.10cm 2。 厚的周边部分具有大于约150微米的宽度和环形尺寸，即径向宽度大于10微米。 碱性区域具有两个连续的杂质部分。 第一杂质部分邻接半导体本体的外围部分的主要优选平面表面，并且在表面处具有至少1×10 19原子/立方厘米的硼的杂质浓度和陡峭的杂质浓度梯度以提供良好的欧姆和 热性能。 第二连续杂质部分在发射极和集电极区域之间的本体的内部部分中，并且具有比第一杂质部分更低的镓和/或铝的杂质浓度较低的杂质浓度梯度。 优选地，通过硼和镓和/或铝的同时扩散来形成基极区的第一和第二杂质部分。

公开(公告)号：US3682700A

公开(公告)日：1972-08-08

申请号：US3682700D

申请日：1968-08-15

Applicant: GALE IND INC

Inventor： GLYPTIS NICHOLAS D

IPC: H01C17/18 ,  H01L21/00 ,  H01L21/48 ,  H05B3/84 ,  H05B33/28 ,  H01B1/06

CPC classification number: H05B3/84 ,  H01C17/18 ,  H01L21/00 ,  H01L21/4846 ,  H05B2203/017 ,  Y10S148/152 ,  Y10S148/157

Abstract: THE METHOD OF IMPARTING ELECTRICAL CONDUCTIVITY TO AN AMORPHOUS NORMALLY NON-CONDUCTING, THERMALLY PLASTICIZABLE, SOLID SUBSTRATE BY ION IMPLATATION COMPRISING MOLECULARLY EXCITING THE SUBSTRATE AT A SURFACE THEREOF TO A MOLECULARLY PLASTIC CONDITION AND APPLYING TO THIS EXCITED SUBSTRATE A COMPOSITION CONTAINING INORGANIC ELECTRICALLY CONDUCTING PARTICLES OF COLLOIDAL SIZE AND SMALLER WITH THE RESULT THAT THE PARTICLES PENTRATED OR IMPLANT THE EXCITED PLASTIC SUBSTRATE AT THE EXCITED SURFACE BETWEEN THE MOLECULES THEREOF AND IMPART ELECTRICAL CONDUCTIVITY TO THE SUBSTRATE, THE CONDUCTIVITY BEING RETAINED WHEN THE EXCITING OF THE SOLID SUBSTRATE CEASES, THE COMPOSITION COMPRISING A CARRIER SOLID THAT IS AN INORGANIC COMPOUND OF AN ELEMENT OF ONE OF GROUPS III, IV, AND V OF THE PERIODIC TABLE, AND N-TYPE IMPURITY INORGANIC COMPOUND OF AN ELEMENT THAT CAN EXIST IN A VALENCE STATE HIGHER THAN THAT OF THE CARRIER ELEMENT, AND A P-TYPE IMPURITY INORGANIC COMPOUND OF AN ELEMENT THAT CAN EXIST IN A VALENCE STATE LOWER THAN OF THE CARRIER ELEMENT, AND THE PRODUCTS RESULTING FROM THESE METHODS.

公开(公告)号：US5648285A

公开(公告)日：1997-07-15

申请号：US533966

申请日：1995-09-26

Applicant: Kiyokazu Ishige

Inventor： Kiyokazu Ishige

IPC: H01L21/8247 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  Y10S148/157

Abstract: In a method for manufacturing a semiconductor memory device including a plurality of field areas, a plurality of electrode areas, a plurality of source areas and drain areas sunrounded by the field areas and the electrode areas, before forming field insulating layers for isolating the source and drain regions, impurities are introduced into the field areas between the source regions, to create an additional source region below the field insulating layer for isolating the source regions. The additional source regions are linked between the source regions.

Abstract translation: 在制造半导体存储器件的方法中，在形成用于隔离源极的场绝缘层之前，包括多个场区域，多个电极区域，由场区域和电极区域包围的多个源极区域和漏极区域，以及 漏极区域，杂质被引入到源极区域之间的场区域中，以在场绝缘层下方产生用于隔离源极区域的附加源极区域。 附加源区域在源区域之间连接。

公开(公告)号：US4987097A

公开(公告)日：1991-01-22

申请号：US486397

申请日：1990-02-28

Applicant: Koichi Nitta ,  Yukie Nishikawa ,  Masayuki Ishikawa ,  Yasuhiko Tsuburai ,  Yoshihiro Kokubun

Inventor： Koichi Nitta ,  Yukie Nishikawa ,  Masayuki Ishikawa ,  Yasuhiko Tsuburai ,  Yoshihiro Kokubun

IPC: H01L33/00 ,  H01S5/20 ,  H01S5/223 ,  H01S5/32 ,  H01S5/323

CPC classification number: H01L33/0062 ,  H01S5/20 ,  H01S5/2231 ,  H01S5/2059 ,  H01S5/321 ,  H01S5/32325 ,  Y10S148/095 ,  Y10S148/157

Abstract: A gain waveguide type semiconductor laser oscillating visible light has an N type GaAs substrate of, and a double-heterostructure provided above the substrate to include an InGaP active layer, and first and second cladding layers sandwiching the active layer. The first cladding layer consists of N type InGaAlP, whereas the second cladding layer consists of P type InGaAlP. A P type InGaP layer is formed as an intermediate band-gap layer on the second cladding layer. An N type GaAs current-blocking layer is formed on the intermediate band-gap layer, and has an elongated waveguide opening. A P type GaAs contact layer is formed to cover the current-blocking layer and the opening. The intermediate band-gap layer has a carrier concentration, in a layer portion being in contact with the opening, high enough to cause a current injected in the oscillation mode to concentrate on the layer portion and has a carrier density, in the remaining layer portion, low enough to suppress or prevent the injected current from spreading thereinto. The layer portion may be formed by additionally doping a selected impurity into the intermediate gap layer by using a presently available impurity diffusion/injection technique.