公开(公告)号：US5643435A

公开(公告)日：1997-07-01

申请号：US673021

申请日：1996-07-01

Applicant: Glenn F. Guhman ,  Madhukar L. Joshi

Inventor： Glenn F. Guhman ,  Madhukar L. Joshi

IPC: B01D53/32 ,  C23C16/44 ,  C23C16/448 ,  C25D11/32 ,  C25D9/00 ,  H01L21/465

CPC classification number: B01D53/326 ,  C23C16/4402 ,  C23C16/4488 ,  Y10S438/935

Abstract: The present invention encompasses a semiconductor processing device having a processing chamber in which is positioned an electrolyte oxygen pump assembly and tubing for transferring an oxygen containing gas from outside the reaction chamber to within the interior of the electrolyte oxygen pump assembly and tubing for removal of the oxygen depleted gas from within the interior of the electrolyte oxygen pump assembly. In addition, the semiconductor processing tool may further have heating elements for heating a semiconductor substrate within the processing chamber independently from heating of the electrolyte.

Abstract translation: 本发明包括具有处理室的半导体处理装置，其中定位有电解质氧泵组件和用于将含氧气体从反应室外部转移到电解氧化泵组件内部的管道和用于移除 来自电解氧气泵组件内部的贫氧气体。 此外，半导体处理工具还可以具有用于独立于电解质的加热来加热处理室内的半导体衬底的加热元件。

公开(公告)号：US4216573A

公开(公告)日：1980-08-12

申请号：US904182

申请日：1978-05-08

Applicant: Madhukar L. Joshi ,  Richard K. Mason ,  Wilbur D. Pricer

Inventor： Madhukar L. Joshi ,  Richard K. Mason ,  Wilbur D. Pricer

IPC: H01L21/336 ,  H01L29/417 ,  H01L29/78 ,  B01J17/00

CPC classification number: H01L29/78

Abstract: A three mask method is provided for making a field effect transistor which includes the use of a first mask for defining first and second spaced apart diffusion regions, each having first and second ends, a second mask for defining a contact region at the first end of the first and second diffusion regions and for defining a protected region at the gate region and source and drain electrodes of the transistor, the protected region extending between the second ends of the first and second diffusion regions, and a third mask for forming a gate electrode within the protected region and contact electrodes in the contact region. The source and drain electrodes are formed between the gate electrode and the first and second diffusion regions by ion implantation techniques. The surfaces of the first and second diffusion regions between the contact electrodes and the second end of the first and second diffusions are oxidized to provide a crossover arrangement for gate electrode wiring, when desired, without requiring additional process steps.

Abstract translation: 提供三掩模方法用于制造场效应晶体管，其包括使用第一掩模来限定第一和第二间隔开的扩散区域，每个第一和第二间隔扩散区域具有第一和第二端，第二掩模，用于限定第一和第二端部处的接触区域 所述第一和第二扩散区域以及用于在所述晶体管的栅极区域和源极和漏极电极处限定保护区域，所述保护区域在所述第一和第二扩散区域的第二端之间延伸，以及用于形成栅电极的第三掩模 在受保护区域内和接触区域中的接触电极。 源极和漏极通过离子注入技术形成在栅电极和第一和第二扩散区之间。 在需要的情况下，在接触电极和第一和第二扩散的第二端之间的第一和第二扩散区域的表面被氧化以提供用于栅极电极布线的交叉布置，而不需要额外的工艺步骤。

公开(公告)号：US4123300A

公开(公告)日：1978-10-31

申请号：US793217

申请日：1977-05-02

Applicant: Madhukar L. Joshi ,  Paul F. Landler ,  Ronald Silverman

Inventor： Madhukar L. Joshi ,  Paul F. Landler ,  Ronald Silverman

IPC: H01L27/10 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/108 ,  H01L29/78 ,  H01L29/58 ,  H01L21/265

CPC classification number: H01L27/10844 ,  H01L21/768 ,  H01L21/8234

Abstract: A method for making high density integrated circuits which utilizes lift-off techniques provides a structure having a single layer of insulating material for both the dielectric of a storage capacitor and the insulator for a gate or control electrode of a switching element. The steps of the method include forming a thin layer of silicon dioxide on a silicon substrate followed by a layer of first doped polysilicon and, optionally, a layer of silicon nitride and then a layer of photoresist. The layers are etched to the silicon dioxide surface with the exception of the portion of the layers overlying a region defined as the gate or control electrode of the switching element. A second layer of doped polysilicon is then deposited over the remaining structure to provide on the silicon dioxide layer a second conductive layer adjacent to but spaced from the first polysilicon layer forming the gate or control electrode. The silicon nitride, when used, is etched away and a strip of conductive metal is placed in contact with the first conductive polysilicon layer after the second doped polysilicon layer has been appropriately oxidized to form an insulating medium over this second polysilicon layer and between the first and second polysilicon layers. Any desired n+ regions may be formed in the silicon substrate by diffusing impurities into the substrate prior to forming the silicon dioxide layer, or the n+ regions may be formed after the silicon dioxide has been formed by using appropriate ion implantation techniques. By employing this method, high density one device memory arrays may be produced by using the first doped polysilicon layer for forming the gate electrode of a field effect transistor and the second doped polysilicon layer as an electrode of the storage capacitor.

Abstract translation: 利用剥离技术制造高密度集成电路的方法提供了一种用于存储电容器的电介质和用于开关元件的栅极或控制电极的绝缘体的单层绝缘材料的结构。 该方法的步骤包括在硅衬底上形成薄层的二氧化硅，接着是第一掺杂多晶硅层，以及任选的氮化硅层，然后是一层光刻胶。 除了覆盖被定义为开关元件的栅极或控制电极的区域的层的部分之外，将层蚀刻到二氧化硅表面。 然后在剩余结构上沉积第二层掺杂多晶硅，以在二氧化硅层上提供与形成栅极或控制电极的第一多晶硅层相邻但间隔开的第二导电层。 氮化硅在使用时被蚀刻掉，并且在第二掺杂多晶硅层被适当地氧化之后，导电金属条被放置成与第一导电多晶硅层接触，以在该第二多晶硅层上和第一多晶硅层之间形成绝缘介质 和第二多晶硅层。 通过在形成二氧化硅层之前将杂质扩散到衬底中，可以在硅衬底中形成任何所需的n +区，或者可以通过使用合适的离子注入技术在形成二氧化硅之后形成n +区。 通过采用该方法，可以通过使用用于形成场效应晶体管的栅电极的第一掺杂多晶硅层和作为存储电容器的电极的第二掺杂多晶硅层来制造高密度一器件存储器阵列。

公开(公告)号：US4049478A

公开(公告)日：1977-09-20

申请号：US638496

申请日：1975-12-08

Applicant: Hitendra N. Ghosh ,  Madhukar L. Joshi ,  Tsu-Hsing Yeh

Inventor： Hitendra N. Ghosh ,  Madhukar L. Joshi ,  Tsu-Hsing Yeh

IPC: H01L21/22 ,  H01L21/223 ,  H01L29/08 ,  H01L21/20

CPC classification number: H01L21/22 ,  H01L21/223 ,  H01L29/0804 ,  Y10S148/04 ,  Y10S148/041 ,  Y10S148/085 ,  Y10S148/157

Abstract: A substantially square N-type impurity distribution profile in a silicon substrate produces much superior dc and ac characteristics in PN junction devices than can be expected from the usual phosphorus distribution profile. Such a square profile is obtained by diffusion of arsenic in the silicon substrate. The sharper impurity gradient allows a relatively low surface concentration to be used for the device. This lower surface concentration relieves precipitation and dislocation problems.

Abstract translation: 在硅衬底中基本上为方形的N型杂质分布曲线在PN结器件中产生比从通常的磷分布曲线预期的更好的直流和交流特性。 通过砷在硅衬底中的扩散来获得这样的正方形。 更尖锐的杂质梯度允许相对低的表面浓度用于器件。 这种较低的表面浓度可以减轻沉淀和脱位问题。

公开(公告)号：US5611898A

公开(公告)日：1997-03-18

申请号：US450063

申请日：1995-05-25

Applicant: Glenn F. Guhman ,  Madhukar L. Joshi

Inventor： Glenn F. Guhman ,  Madhukar L. Joshi

IPC: B01D53/32 ,  C23C16/44 ,  C23C16/448 ,  C25B9/00 ,  C23C16/00

CPC classification number: B01D53/326 ,  C23C16/4402 ,  C23C16/4488 ,  Y10S438/935

Abstract: The present invention encompasses a semiconductor processing device having a processing chamber in which is positioned an electrolyte oxygen pump assembly and tubing for transferring an oxygen containing gas from outside the reaction chamber to within the interior of the electrolyte oxygen pump assembly and tubing for removal of the oxygen depleted gas from within the interior of the electrolyte oxygen pump assembly. In addition, the semiconductor processing tool may further have heating elements for heating a semiconductor substrate within the processing chamber independently from heating of the electrolyte.

Abstract translation: 本发明包括具有处理室的半导体处理装置，其中定位有电解质氧泵组件和用于将含氧气体从反应室外部转移到电解氧化泵组件内部的管道和用于移除 来自电解氧气泵组件内部的贫氧气体。 此外，半导体处理工具还可以具有用于独立于电解质的加热来加热处理室内的半导体衬底的加热元件。

公开(公告)号：US4168536A

公开(公告)日：1979-09-18

申请号：US811812

申请日：1977-06-30

Applicant: Madhukar L. Joshi ,  Wilbur D. Pricer

Inventor： Madhukar L. Joshi ,  Wilbur D. Pricer

IPC: G11C11/419 ,  G11C11/403 ,  G11C11/405 ,  G11C11/42 ,  G11C11/24

CPC classification number: G11C11/403

Abstract: A memory is produced which has a series circuit including charge storage means, an impedance and switching means and an amplifier having an input connected to the series circuit at a point between the charge storage means and the impedance and an output coupled to a bit/sense line. The switching means is controlled by a pulse from a word line. The series circuit interconnects the bit/sense line and a point of reference potential. In a preferred embodiment, the switching means is a first field effect transistor having its gate electrode connected to the word line and the amplifier is a second field effect transistor having its gate electrode connected to the series circuit at a point between the charge storage means and the impedance and having one of its current carrying electrodes coupled to the bit/sense line and its other current carrying electrode coupled to a point of reference potential.

Abstract translation: 产生具有串联电路的存储器，其包括电荷存储装置，阻抗和开关装置以及在电荷存储装置和阻抗之间的点处连接到串联电路的输入端和耦合到位/感测的输出的放大器 线。 开关装置由字线的脉冲控制。 串联电路将位/检测线和参考电位互连。 在优选实施例中，开关装置是其栅电极连接到字线的第一场效应晶体管，放大器是第二场效应晶体管，其栅电极连接到电荷存储装置和 该阻抗并且具有耦合到比特/感测线及其另一个载流电极的一个其载流电极耦合到参考电位点。