公开(公告)号：US08058902B1

公开(公告)日：2011-11-15

申请号：US12813527

申请日：2010-06-11

Applicant: Sahil Khurana ,  Vivek Singhal ,  Yogesh Darwhekar

Inventor： Sahil Khurana ,  Vivek Singhal ,  Yogesh Darwhekar

IPC: G06F7/38 ,  G06F1/12 ,  G06F13/42 ,  H03K19/0175 ,  H01L5/00 ,  H01L7/00

CPC classification number: G06F1/12

Abstract: A circuit for aligning input signals includes a clock generating circuit (CGC) responsive to first signal and second signal to generate a clock signal. A first flip flop and a second flip flop, coupled to the CGC, are responsive to first type of edge of the clock signal to output the first signal and the second signal. A finite state machine (FSM), coupled to the CGC, the first flip flop and the second flip flop, is responsive to second type of edge of the clock signal to detect early arrival of one of the first signal and the second signal with respect to each other, and to generate first control signal and second control signal. A first programmable delay element and a second programmable delay element, coupled to the FSM, delays first input signal based on the first control signal and second input signal based on the second control signal.

Abstract translation: 用于对准输入信号的电路包括响应于第一信号和第二信号的时钟发生电路（CGC）以产生时钟信号。 耦合到CGC的第一触发器和第二触发器响应于时钟信号的第一类型的边沿以输出第一信号和第二信号。 耦合到CGC的第一触发器和第二触发器的有限状态机（FSM）响应于时钟信号的第二类型的边缘来检测第一信号和第二信号中的一个的早期到达，相对于 并且产生第一控制信号和第二控制信号。 耦合到FSM的第一可编程延迟元件和第二可编程延迟元件基于第一控制信号和基于第二控制信号的第二输入信号来延迟第一输入信号。

公开(公告)号：US07352207B2

公开(公告)日：2008-04-01

申请号：US11239944

申请日：2005-09-30

Applicant: Akhil K. Garlapati ,  Axel Thomsen

Inventor： Akhil K. Garlapati ,  Axel Thomsen

IPC: H03K19/094 ,  H03K19/0175 ,  H01L5/00

CPC classification number: H03F3/45188 ,  H03F3/3061 ,  H03F3/45654 ,  H03F3/45708

Abstract: A complementary metal-oxide semiconductor output driver provides a differential output signal having a particular differential voltage swing and a particular common mode voltage to a differential output node for various types of load circuits coupled to the differential output node. The load circuit may have any impedance within a particular impedance range. A current source provides a current with a variable current component that adjusts the differential voltage swing of the differential output signal. A common mode feedback circuit adjusts the common mode voltage of the differential output signal by sourcing current to the differential output node or sinking current from the differential output node. At least a portion of a current flowing into a load circuit coupled to the differential node is provided by the current source, thereby reusing current from the current source.

Abstract translation: 互补金属氧化物半导体输出驱动器为耦合到差分输出节点的各种类型的负载电路提供具有特定差分电压摆幅和特定共模电压的差分输出信号到差分输出节点。 负载电路可以在特定阻抗范围内具有任何阻抗。 电流源为电流提供调节差分输出信号的差分电压摆幅的可变电流分量。 共模反馈电路通过向差分输出节点提供电流或从差分输出节点吸收电流来调整差分输出信号的共模电压。 流过耦合到差分节点的负载电路的电流的至少一部分由电流源提供，从而重新使用来自电流源的电流。

公开(公告)号：US4261781A

公开(公告)日：1981-04-14

申请号：US7857

申请日：1979-01-31

Applicant: Harold D. Edmonds ,  Vincent J. Lyons ,  Gary Markovits

Inventor： Harold D. Edmonds ,  Vincent J. Lyons ,  Gary Markovits

IPC: H01L21/52 ,  B28D1/00 ,  B28D5/00 ,  H01L21/00 ,  H01L21/02 ,  H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/78 ,  H01L23/492 ,  H01L5/00

CPC classification number: H01L23/4926 ,  B28D1/005 ,  B28D5/0094 ,  H01L21/302 ,  H01L21/3043 ,  H01L21/67092 ,  H01L21/78 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10S148/028 ,  Y10T156/1059

Abstract: Compound semiconductor bodies are formed by bonding a layer of supporting material to the two opposite faces of a semiconductor wafer and then cutting the semiconductor wafer into two parts in a plane parallel to said faces. The cut surface of each part is then polished.

Abstract translation: 通过将支撑材料层粘合到半导体晶片的两个相对面，然后在与所述面平行的平面中将半导体晶片切割成两部分而形成复合半导体本体。 然后对每个部件的切割表面进行抛光。

公开(公告)号：US4081821A

公开(公告)日：1978-03-28

申请号：US642551

申请日：1975-12-19

Applicant: Jozef Cornu ,  Roland Sittig

Inventor： Jozef Cornu ,  Roland Sittig

IPC: H01L29/36 ,  H01L29/74 ,  H01L1/04 ,  H01L3/00 ,  H01L5/00

CPC classification number: H01L29/7432 ,  H01L29/36

Abstract: A bistable semiconductor component for high frequencies with a semiconductor chip includes a sequence of at least four zones of alternating opposed types of conductivity. The outer zones form the emitter zones and are more heavily doped than the two inner zones. The base zones are so doped that with a voltage V.sub.R smaller than or at most equal to the maximum inverse voltage V.sub.RS applied in the reverse direction across the two emitter zones, the shortest distance W between the two blocking layers formed at the two outer junctions is less than the diffusion length L.sub.B of the charge carriers in the base zones.

Abstract translation: 具有半导体芯片的用于高频的双稳态半导体部件包括具有交替相对导电类型的至少四个区域的序列。 外部区域形成发射区，并且比两个内部区域更重掺杂。 基极区是这样掺杂的，其电压VR小于或者最多等于穿过两个发射极区域的相反方向施加的最大反向电压VRS，形成在两个外部接头处的两个阻挡层之间的最短距离W是 小于基区中电荷载体的扩散长度LB。

公开(公告)号：US4035823A

公开(公告)日：1977-07-12

申请号：US727733

申请日：1976-09-29

Applicant: James F. Marshall

Inventor： James F. Marshall

IPC: G01L9/00 ,  H01L29/84 ,  H04R23/00 ,  B01J17/00 ,  H01L5/00 ,  H01L29/96

CPC classification number: G01L9/0054 ,  G01L9/0042 ,  H01L29/84 ,  H04R23/006

Abstract: Semiconductor material stress sensors are provided where the sensing resistors therein have good electrical stability while being sufficiently protected without degrading sensor performance. This is accomplished through control of the locations of the maximum concentrations of the resistor dopant.

Abstract translation: 提供半导体材料应力传感器，其中感测电阻器具有良好的电气稳定性，同时充分保护，而不降低传感器性能。 这通过控制电阻器掺杂剂的最大浓度的位置来实现。

公开(公告)号：US3896479A

公开(公告)日：1975-07-22

申请号：US44754774

申请日：1974-03-04

Applicant: BELL TELEPHONE LABOR INC

Inventor： DI LORENZO JAMES VINCENT ,  ROZGONYI GEORGE ARTHUR

IPC: H01L21/60 ,  H01L23/36 ,  H01L29/864 ,  H01L5/00

CPC classification number: H01L24/33 ,  H01L23/36 ,  H01L24/48 ,  H01L24/83 ,  H01L29/864 ,  H01L2224/4847 ,  H01L2224/8319 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12041 ,  H01L2924/3011 ,  Y10S148/02 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Substrate tensile stresses resulting from the combination of an electroplated gold or silver heat sink with a metal contact on III-V semiconductor devices, such as GaAs IMPATT diodes, may be substantially compensated by interposing a layer of tungsten under compressive stress between the contact layer and the heat sink. Since gold or silver is not easily plated on tungsten, a thin layer of platinum is deposited over the tungsten layer prior to forming the heat sink.

公开(公告)号：US3893160A

公开(公告)日：1975-07-01

申请号：US39217473

申请日：1973-08-28

Applicant: LICENTIA GMBH

Inventor： BOTZENHARDT LEONHARD

IPC: H01L29/43 ,  H01L21/00 ,  H01L21/28 ,  H01L23/532 ,  H01L3/00 ,  H01L5/00

CPC classification number: H01L23/53242 ,  H01L21/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A resistive connecting contact for a silicon semiconductor component comprises, on the semiconductor body, a layer sequence platinum silicide-titanium-molybdenum-gold. The invention also includes a method of making such a connecting contact.

Abstract translation: 用于硅半导体部件的电阻性连接接点包括在半导体本体上的层序列铂硅化钛 - 钛 - 钼 - 金。 本发明还包括制造这种连接接触的方法。

公开(公告)号：US3893159A

公开(公告)日：1975-07-01

申请号：US44597174

申请日：1974-02-26

Applicant: RCA CORP

Inventor： MARTIN IRVING EDWIN

IPC: H01L23/66 ,  H01L25/16 ,  H01L3/00 ,  H01L5/00

CPC classification number: H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L25/16 ,  H01L2223/6644 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/45099

Abstract: The device comprises a plurality of side by side transistor cells individually connected by a plurality of lead wires in a side-by-side lead wire array having a central axis. For reducing the effects of variations of mutual inductance among the various lead wires, and for providing a more uniform temperature from cell to cell, the individual lead wires are designed to have a self-inductance the magnitude of which is directly related to the distance of the particular lead wire from the central axis.

Abstract translation: 该器件包括多个并排晶体管单元，该多个并联晶体管单元由具有中心轴的并排引线阵列中的多根引线单独连接。 为了减少各种引线之间的互感变化的影响，并且为了从单元到单元提供更均匀的温度，单独的导线被设计成具有自感，其大小与其距离直接相关 特定的导线从中心轴线。

公开(公告)号：US3883889A

公开(公告)日：1975-05-13

申请号：US46073674

申请日：1974-04-15

Applicant: MICRO POWER SYSTEMS INC

Inventor： HALL JOHN H

IPC: C23C16/30 ,  H01L21/314 ,  H01L29/00 ,  H01L5/00 ,  H01L3/00

CPC classification number: H01L21/3145 ,  C23C16/308 ,  H01L29/00 ,  Y10S148/043 ,  Y10S148/053 ,  Y10S148/118

Abstract: A protective layer for use in the manufacture of semiconductor devices and circuits and for thereafter protecting and passivating the devices comprising a combination of silicon, oxygen and nitrogen in selected atomic proportions.

Abstract translation: 一种保护层，用于制造半导体器件和电路，并用于之后保护和钝化包含选定原子比例的硅，氧和氮组合的器件。

公开(公告)号：US3878554A

公开(公告)日：1975-04-15

申请号：US39175873

申请日：1973-08-27

Applicant: FUJITSU LTD

Inventor： MIKOME KOICHI ,  MATSUDA YOSHIHIRO ,  NAMIKI YOSHIYUKI

IPC: H01L23/482 ,  H01L5/00

CPC classification number: H01L23/4822 ,  H01L24/01 ,  H01L2924/01327 ,  H01L2924/12036 ,  H01L2924/00

Abstract: A semiconductor device wherein a beam lead connected to each wiring layer is all formed on a silicon nitride film of a semiconductor wafer surface in a semiconductor device having a multilayer wiring structure on a semiconductor basic board.

Abstract translation: 在半导体基板上具有多层布线结构的半导体器件的半导体晶片表面的氮化硅膜上，全部形成与各布线层连接的光束引线的半导体器件。