公开(公告)号：US08058902B1

公开(公告)日：2011-11-15

申请号：US12813527

申请日：2010-06-11

Applicant: Sahil Khurana ,  Vivek Singhal ,  Yogesh Darwhekar

Inventor： Sahil Khurana ,  Vivek Singhal ,  Yogesh Darwhekar

IPC: G06F7/38 ,  G06F1/12 ,  G06F13/42 ,  H03K19/0175 ,  H01L5/00 ,  H01L7/00

CPC classification number: G06F1/12

Abstract: A circuit for aligning input signals includes a clock generating circuit (CGC) responsive to first signal and second signal to generate a clock signal. A first flip flop and a second flip flop, coupled to the CGC, are responsive to first type of edge of the clock signal to output the first signal and the second signal. A finite state machine (FSM), coupled to the CGC, the first flip flop and the second flip flop, is responsive to second type of edge of the clock signal to detect early arrival of one of the first signal and the second signal with respect to each other, and to generate first control signal and second control signal. A first programmable delay element and a second programmable delay element, coupled to the FSM, delays first input signal based on the first control signal and second input signal based on the second control signal.

Abstract translation: 用于对准输入信号的电路包括响应于第一信号和第二信号的时钟发生电路（CGC）以产生时钟信号。 耦合到CGC的第一触发器和第二触发器响应于时钟信号的第一类型的边沿以输出第一信号和第二信号。 耦合到CGC的第一触发器和第二触发器的有限状态机（FSM）响应于时钟信号的第二类型的边缘来检测第一信号和第二信号中的一个的早期到达，相对于 并且产生第一控制信号和第二控制信号。 耦合到FSM的第一可编程延迟元件和第二可编程延迟元件基于第一控制信号和基于第二控制信号的第二输入信号来延迟第一输入信号。