公开(公告)号：US5510630A

公开(公告)日：1996-04-23

申请号：US138908

申请日：1993-10-18

申请人： Anant K. Agarwal ,  Richard R. Siergiej ,  Charles D. Brandt ,  Marvin H. White

发明人： Anant K. Agarwal ,  Richard R. Siergiej ,  Charles D. Brandt ,  Marvin H. White

IPC分类号： H01L21/82 ,  H01L27/115 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L29/04 ,  H01L29/48

CPC分类号： H01L29/1608 ,  H01L21/8213 ,  H01L27/115 ,  H01L29/7838

摘要： A non-volatile random access memory (NVRAM) cell that utilizes a simple, single-transistor DRAM cell configuration. The present NVRAM employs an enhancement mode nMOS transistor made as an accumulation mode transistor. The transistor has an n-type silicon carbide channel layer on a p-type silicon carbide buffer layer, with the channel and buffer layers being on a highly resistive silicon carbide substrate. The transistor also has n+ source and drain contact regions on the channel layer. A polysilicon/oxide/metal capacitor is preferably used which has a very low leakage current. Furthermore, this type of capacitor can be stacked on top of the transistor to save area and achieve high cell density. It is preferred to use a non-reentrant (edgeless) gate transistor structure to further reduce edge effects.

摘要翻译： 利用简单的单晶体管DRAM单元配置的非易失性随机存取存储器（NVRAM）单元。 目前的NVRAM采用了作为累积模式晶体管制成的增强型nMOS晶体管。 晶体管在p型碳化硅缓冲层上具有n型碳化硅沟道层，其中沟道和缓冲层位于高电阻碳化硅衬底上。 晶体管还在沟道层上具有n +源极和漏极接触区域。 优选使用具有非常低的漏电流的多晶硅/氧化物/金属电容器。 此外，这种类型的电容器可以堆叠在晶体管的顶部以节省面积并实现高电池密度。 优选使用不可重入（无边缘）栅极晶体管结构来进一步减少边缘效应。

公开(公告)号：US5479040A

公开(公告)日：1995-12-26

申请号：US270090

申请日：1994-07-01

申请人： Michael C. Smayling ,  Luciano Talamonti

发明人： Michael C. Smayling ,  Luciano Talamonti

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H02M3/07 ,  H01L27/02 ,  H01L29/48 ,  H01L29/56 ,  H01L29/64

CPC分类号： H01L27/11517 ,  H01L27/115 ,  H02M3/073

摘要： A charge pump (10) uses Schottky diodes (12) coupled to clock signals (o.sub.1 and o.sub.2) via respective capacitors (14a-d). Regulation and control circuitry 18 provides a stable voltage output and controls the clock circuitry (16).

摘要翻译： 电荷泵（10）使用通过相应电容器（14a-d）耦合到时钟信号（o1和o2）的肖特基二极管（12）。 调节和控制电路18提供稳定的电压输出并控制时钟电路（16）。

公开(公告)号：US5408129A

公开(公告)日：1995-04-18

申请号：US183573

申请日：1994-01-18

申请人： Michael Farmwald ,  Mark Horowitz

发明人： Michael Farmwald ,  Mark Horowitz

IPC分类号： G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00 ,  H01L29/48 ,  H01L29/44 ,  H01L29/52 ,  H01L29/60

CPC分类号： G11C7/1066 ,  G06F11/006 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

摘要： The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

摘要翻译： 本发明包括一个包括至少两个半导体器件的存储器子系统，包括连接到总线的至少一个存储器件，其中总线包括用于承载所有存储器件所需的所有地址，数据和控制信息的多条总线 ，其中控制信息包括设备选择信息，并且总线具有比单个地址中的位数少得多的总线，并且总线承载设备选择信息，而不需要直接连接到各个设备的单独的设备选择线 。 本发明还包括用于主设备和从设备在总线上通信的协议，以及用于每个设备中的寄存器以区分每个设备并允许总线请求被引导到单个或所有设备的协议。 本发明包括对现有技术设备的修改，以允许它们实现本发明的新特征。 在一个优选实施方式中，8个总线数据线和一个AddressValid总线携带地址，数据和控制信息，用于高达40位宽的存储器地址。

公开(公告)号：US5397907A

公开(公告)日：1995-03-14

申请号：US223781

申请日：1994-04-06

申请人： Yong H. Lee

发明人： Yong H. Lee

IPC分类号： H01L21/20 ,  H01L21/285 ,  H01L21/338 ,  H01L29/06 ,  H01L29/10 ,  H01L29/812 ,  H01L29/48 ,  H01L29/56 ,  H01L29/64

CPC分类号： H01L29/66863 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/28587 ,  H01L29/0649 ,  H01L29/1029 ,  H01L29/812

摘要： A MESFET which includes a semi-insulating substrate, e.g., a GaAs substrate, an insulating layer formed on a portion of the upper surface of the substrate, a first semiconductor layer formed on the upper surface of the substrate adjacent to opposite sides of the insulating layer, the first semiconductor layer having sidewalls defining a void therein, a nitride layer formed on a portion of the upper surface of the insulating layer, an oxide layer formed on the nitride layer, a second semiconductor layer formed on the sidewalls of the first semiconductor layer and in covering relationship to the void, a gate electrode formed on at least a portion of the upper surface of the second semiconductor layer, and, source and drain electrodes formed on the upper surface of the first semiconductor layer, on opposite sides of the gate electrode.

摘要翻译： 一种MESFET，其包括半绝缘衬底，例如GaAs衬底，形成在衬底的上表面的一部分上的绝缘层;第一半导体层，形成在衬底的上表面上，与绝缘体的相对侧相邻 层，其中具有限定空隙的第一半导体层，形成在绝缘层的上表面的一部分上的氮化物层，形成在氮化物层上的氧化物层，形成在第一半导体的侧壁上的第二半导体层 层，并且覆盖与空隙的关系，形成在第二半导体层的上表面的至少一部分上的栅电极以及形成在第一半导体层的上表面上的源电极和漏电极， 栅电极。

公开(公告)号：US5389817A

公开(公告)日：1995-02-14

申请号：US158358

申请日：1993-11-29

申请人： Tsutomu Imamura ,  Isao Baba

发明人： Tsutomu Imamura ,  Isao Baba

IPC分类号： H01L21/52 ,  H01L23/31 ,  H01L23/495 ,  H01L29/48 ,  H01L29/44 ,  H01L29/52 ,  H01L29/60

CPC分类号： H01L23/49513 ,  H01L23/3107 ,  H01L23/49503 ,  H01L24/32 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/078 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/351

摘要： A plastic package type semiconductor device comprises: a die pad consisting of a plurality of parts; a tab lead consisting of a plurality of parts holding the die pad; a flat type Jumper lead formed between the parts of the die pad; an electrical insulating type insulating film formed on the die pad; a semiconductor chip bonded on the insulating film by an adhesive; and a plastic mold as a plastic package for molding the die pad, the tab lead, the flat type Jumper lead, the insulating file, and the semiconductor device in the plastic mold, whereby the semiconductor chip is Insulated electrically from the die pad. In addition, a SOJ plastic package type semiconductor device has a configuration without the Jumper lead described above.

摘要翻译： 塑料封装型半导体器件包括：由多个部件组成的管芯焊盘; 由保持所述管芯焊盘的多个部件组成的突片引线; 形成在芯片焊盘的部分之间的扁平型跳线; 形成在所述芯片焊盘上的电绝缘型绝缘膜; 通过粘合剂粘结在绝缘膜上的半导体芯片; 以及塑料模具，用于在塑料模具中成型模具垫，突片引线，平面型跳线，绝缘材料和半导体器件的塑料封装，由此半导体芯片与管芯焊盘电绝缘。 此外，SOJ塑料封装型半导体器件具有不具有上述跳线的构造。

公开(公告)号：US5389799A

公开(公告)日：1995-02-14

申请号：US74541

申请日：1993-06-11

申请人： Tsutomu Uemoto

发明人： Tsutomu Uemoto

IPC分类号： H01L29/08 ,  H01L29/24 ,  H01L33/00 ,  H01L33/34 ,  H01L29/48 ,  H01L23/48 ,  H01L29/161 ,  H01L29/167

CPC分类号： H01L33/343 ,  H01L29/0847 ,  H01L29/1608

摘要： Disclosed is a semiconductor device such as a light emitting diode, a MOS transistor, a Schottky diode, and CCD. The semiconductor device comprises a SiC layer of a first conductivity type and another SiC layer of a second conductivity type. At least one of the SiC layers of the first and second conductivity types is doped with at least one element selected from the group consisting of Cr, Mo and W.

摘要翻译： 公开了诸如发光二极管，MOS晶体管，肖特基二极管和CCD的半导体器件。 半导体器件包括第一导电类型的SiC层和第二导电类型的另一SiC层。 第一和第二导电类型的至少一个SiC层掺杂有选自Cr，Mo和W中的至少一种元素。

公开(公告)号：US5376809A

公开(公告)日：1994-12-27

申请号：US192305

申请日：1994-02-04

申请人： Yutaka Hayashi ,  Masaaki Sato ,  Yoshiki Maeyashiki

发明人： Yutaka Hayashi ,  Masaaki Sato ,  Yoshiki Maeyashiki

IPC分类号： H01L29/74 ,  H01L29/744 ,  H01L29/747 ,  H01L29/861 ,  H01L29/87 ,  H01L29/48 ,  H01L29/90

CPC分类号： H01L29/87

摘要： A surge protection device for absorbing surges of either polarity has a second region forming a first pn junction with a first region, a third region capable of injecting first minority carriers into the second region, a fourth region forming a second pn junction with the first region and a fifth region capable of injecting second minority carriers into the fourth region. The surfaces of the fourth region and the fifth region and a first Schottky junction with respect to the first region are in mutual electrical connection with a first ohmic electrode, while the surfaces of the second region and the third region and a second Schottky junction with respect to the first region are in mutual electrical connection with a second ohmic electrode. During the initial stage when a surge voltage applied across the first and second electrodes is in a transient rising state, the dV/dt immunity is increased by majority carrier current flowing into the first region through the Schottky junction forward biased owing to the surge polarity and charging the junction capacitance of the reverse biased pn junction.

摘要翻译： 用于吸收任一极性的浪涌的浪涌保护装置具有形成与第一区域的第一pn结的第二区域，能够将第一少数载流子注入第二区域的第三区域，与第一区域形成第二pn结的第四区域 以及能够将第二少数载体注入第四区域的第五区域。 第四区域和第五区域的表面和相对于第一区域的第一肖特基结与第一欧姆电极相互电连接，而第二区域和第三区域的表面和第二肖特基结的相对于 到第一区域与第二欧姆电极相互电连接。 在施加在第一和第二电极两端的浪涌电压处于瞬态上升状态的初始阶段，由于浪涌极性，通过肖特基结正向偏置流入第一区域的多数载流子电流使得dV / dt抗扰度增加， 充电反向偏置pn结的结电容。

公开(公告)号：US5373191A

公开(公告)日：1994-12-13

申请号：US998856

申请日：1992-12-30

申请人： Toshiyuki Usagawa ,  Yoshinori Imamura ,  Hidekazu Okuhira ,  Shigeo Goto ,  Masayoshi Kobayashi ,  Shinichiro Takatani

发明人： Toshiyuki Usagawa ,  Yoshinori Imamura ,  Hidekazu Okuhira ,  Shigeo Goto ,  Masayoshi Kobayashi ,  Shinichiro Takatani

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L21/335 ,  H01L21/337 ,  H01L21/338 ,  H01L21/60 ,  H01L21/8252 ,  H01L23/485 ,  H01L29/812 ,  H01L29/80 ,  H01L23/48 ,  H01L29/06 ,  H01L29/48

CPC分类号： H01L21/76897 ,  H01L21/28587 ,  H01L21/8252 ,  H01L23/485 ,  H01L29/66318 ,  H01L29/66462 ,  H01L29/66863 ,  H01L29/66871 ,  H01L29/66924 ,  H01L29/8128 ,  H01L2924/0002

摘要： Source and drain electrode metals of a field effect transistor having a recessed gate electrode metal are directly connected to a high impurity concentration semiconductor layer which faces the gate electrode metal through an insulator film which defines the side wall of the recess. The source and drain electrode metals may be disposed so as to face the gate electrode metal through the side insulator film. With this arrangement, it is possible to lower the parasitic resistance between the gate electrode and another electrode of the field effect transistor, to lower the contact resistance between a semiconductor layer and the source and drain electrodes, to reduce the capacitance of the recess gate electrode and to increase the source-gate breakdown voltage, advantageously. The above-described arrangement is particularly suitable for a transistor employing a compound semiconductor, and can also be applied to semiconductor devices other than field effect transistors. Such semiconductor devices can readily be produced by forming a gate electrode metal with a self-alignment process using the lift-off method.

摘要翻译： 具有凹陷栅电极金属的场效应晶体管的源电极和漏电极金属通过限定凹部的侧壁的绝缘膜直接连接到面向栅电极金属的高杂质浓度半导体层。 源电极和漏电极金属可以通过侧绝缘膜设置成面对栅电极金属。 通过这种布置，可以降低场效应晶体管的栅电极和另一电极之间的寄生电阻，以降低半导体层与源电极和漏电极之间的接触电阻，以减小凹陷栅电极的电容 并且有利地增加源极栅极击穿电压。 上述布置特别适用于采用化合物半导体的晶体管，并且还可以应用于场效应晶体管以外的半导体器件。 这种半导体器件可以容易地通过使用剥离法形成具有自对准工艺的栅电极金属来制造。

公开(公告)号：US5371382A

公开(公告)日：1994-12-06

申请号：US874637

申请日：1992-04-27

申请人： Vasudev Venkatesan ,  Dale G. Thompson ,  Kalyankumar Das

发明人： Vasudev Venkatesan ,  Dale G. Thompson ,  Kalyankumar Das

IPC分类号： H01L21/203 ,  H01L21/04 ,  H01L21/28 ,  H01L29/16 ,  H01L29/47 ,  H01L29/861 ,  H01L45/00 ,  H01L29/161 ,  H01L29/20 ,  H01L29/48

CPC分类号： H01L29/1602 ,  H01L21/0435 ,  H01L29/47

摘要： A rectifying contact for use at high temperatures includes a semiconducting diamond layer and a doped amorphous silicon layer thereon. The amorphous silicon layer may be doped with either a p-type or n-type dopant. The semiconducting diamond may be a doped polycrystalline diamond layer or a natural IIb single crystal diamond. The amorphous silicon layer may be formed by sputter deposition from doped silicon targets. A subsequent heating of the thus formed rectifying contact lowers the forward resistance of the contact by activating additional dopant atoms within the amorphous silicon layer.

摘要翻译： 在高温下使用的整流接触件包括半导体金刚石层和其上的掺杂非晶硅层。 非晶硅层可以掺杂有p型或n型掺杂剂。 半导体金刚石可以是掺杂多晶金刚石层或天然IIb单晶金刚石。 可以通过从掺杂的硅靶的溅射沉积形成非晶硅层。 由此形成的整流接触的随后的加热通过激活非晶硅层内的附加掺杂剂原子来降低接触的正向电阻。

公开(公告)号：US5352908A

公开(公告)日：1994-10-04

申请号：US145307

申请日：1993-11-03

申请人： Koji Kobashi ,  Koichi Miyata ,  Kozo Nishimura

发明人： Koji Kobashi ,  Koichi Miyata ,  Kozo Nishimura

IPC分类号： H01L29/16 ,  H01L29/47 ,  H01L29/86 ,  H01L29/872 ,  H01L29/48

CPC分类号： H01L29/1602 ,  H01L29/872

摘要： A diamond Schottky diode including an electrically conductive substrate, a multi-layer structure of a semiconducting diamond layer and an insulating diamond layer, and a metal electrode. This diode has a greater potential barrier under a reversed bias and hence exhibits better rectifying characteristics with a smaller reverse current.

摘要翻译： 包括导电衬底，半导体金刚石层和绝缘金刚石层的多层结构的金刚石肖特基二极管和金属电极。 该二极管在反向偏置下具有更大的势垒，因此具有较小的反向电流的整流特性。