公开(公告)号：US07042007B2

公开(公告)日：2006-05-09

申请号：US10824426

申请日：2004-04-15

Applicant: Takatoshi Yasui ,  Atsuhiro Kajiya

Inventor： Takatoshi Yasui ,  Atsuhiro Kajiya

IPC: H01L23/58

CPC classification number: H01L22/34 ,  H01L27/088 ,  H01L2924/0002 ,  Y10S257/919 ,  H01L2924/00

Abstract: A single evaluation portion is formed by disposing a plurality of MIS transistors used for evaluation having substantially the same structure as that of an actually used MIS transistor. In the evaluation portion, the respective source regions, drain regions, and gate electrodes of the MIS transistors used for evaluation are electrically connected in common to a source pad, a drain pad, and a gate pad, respectively. If the effective gate width of the single evaluation portion exceeds a given value, variations in characteristics evaluated by the evaluation portion approach variations in the characteristics of the entire semiconductor device. The accuracy of evaluating the characteristics of the semiconductor device can thus be improved by using the evaluation portion.

Abstract translation: 单个评估部分通过设置用于评估的多个MIS晶体管形成，其具有与实际使用的MIS晶体管基本相同的结构。 在评估部分中，用于评估的MIS晶体管的各个源极区域，漏极区域和栅极电极分别电连接到源极焊盘，漏极焊盘和栅极焊盘。 如果单个评估部分的有效栅极宽度超过给定值，则由评估部分评估的特性的变化导致整个半导体器件的特性的变化。 因此，可以通过使用评价部来提高评价半导体装置的特性的精度。

公开(公告)号：US08471341B2

公开(公告)日：2013-06-25

申请号：US12712890

申请日：2010-02-25

Applicant: Yoshihiro Sato ,  Atsuhiro Kajiya

Inventor： Yoshihiro Sato ,  Atsuhiro Kajiya

IPC: H01L27/092

CPC classification number: H01L21/823842 ,  H01L21/823807 ,  H01L29/513 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7843

Abstract: A semiconductor device includes a first MIS transistor formed on a first active region, and a second MIS transistor formed on a second active region. The first MIS transistor includes a first gate insulating film, and a first gate electrode including a first metal film and a first silicon film. The second MIS transistor includes a second gate insulating film, and a second gate electrode including the first metal film, a second metal film, and a second silicon film.

Abstract translation: 半导体器件包括形成在第一有源区上的第一MIS晶体管和形成在第二有源区上的第二MIS晶体管。 第一MIS晶体管包括第一栅极绝缘膜和包括第一金属膜和第一硅膜的第一栅电极。 第二MIS晶体管包括第二栅极绝缘膜和包括第一金属膜，第二金属膜和第二硅膜的第二栅电极。

公开(公告)号：US20080042214A1

公开(公告)日：2008-02-21

申请号：US11892053

申请日：2007-08-20

Applicant: Daisaku Ikoma ,  Atsuhiro Kajiya ,  Katsuhiro Ootani ,  Kyoji Yamashita

Inventor： Daisaku Ikoma ,  Atsuhiro Kajiya ,  Katsuhiro Ootani ,  Kyoji Yamashita

IPC: H01L27/092 ,  H01L29/78

CPC classification number: H01L21/76895 ,  H01L21/823475 ,  H01L27/0207

Abstract: A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.

Abstract translation: 半导体器件包括半导体衬底; 扩散区，其形成在半导体衬底中并用作用于形成MIS晶体管的区域; 围绕扩散区域的元件隔离区域; 形成在扩散区域和元件隔离区域两侧的至少一个栅极导体膜包括位于扩散区域上的栅极电极部分和位于元件隔离区域上的栅极互连部件，并且栅极长度具有恒定的尺寸 方向; 以及覆盖所述栅电极的层间绝缘膜。 半导体器件还包括通过层间绝缘膜的栅极接触，连接到栅极互连部分，并且具有大于栅极互连部分的栅极长度方向的尺寸。

公开(公告)号：US07279727B2

公开(公告)日：2007-10-09

申请号：US11148208

申请日：2005-06-09

Applicant: Daisaku Ikoma ,  Atsuhiro Kajiya ,  Katsuhiro Ootani ,  Kyoji Yamashita

Inventor： Daisaku Ikoma ,  Atsuhiro Kajiya ,  Katsuhiro Ootani ,  Kyoji Yamashita

IPC: H01L27/10

CPC classification number: H01L21/76895 ,  H01L21/823475 ,  H01L27/0207

Abstract: A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.

Abstract translation: 半导体器件包括半导体衬底; 扩散区，其形成在半导体衬底中并用作用于形成MIS晶体管的区域; 围绕扩散区域的元件隔离区域; 形成在扩散区域和元件隔离区域两侧的至少一个栅极导体膜包括位于扩散区域上的栅极电极部分和位于元件隔离区域上的栅极互连部件，并且栅极长度具有恒定的尺寸 方向; 以及覆盖所述栅电极的层间绝缘膜。 半导体器件还包括通过层间绝缘膜的栅极接触，连接到栅极互连部分，并且具有大于栅极互连部分的栅极长度方向的尺寸。

公开(公告)号：US20070018251A1

公开(公告)日：2007-01-25

申请号：US11489539

申请日：2006-07-20

Applicant: Junji Hirase ,  Atsuhiro Kajiya

Inventor： Junji Hirase ,  Atsuhiro Kajiya

IPC: H01L29/94

CPC classification number: H01L21/823412 ,  H01L21/32155 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/7845

Abstract: In a MIEET, an impurity which changes a lattice constant is introduced into part of a gate electrode located on an isolation region. A stress which is generated in part of the gate electrode as a starting point and improves the mobility of carries is applied to a channel region with the part of the gate electrode.

Abstract translation: 在MIEET中，改变晶格常数的杂质被引入到位于隔离区上的栅电极的一部分中。 在栅电极的一部分中产生的作为起点并且提高载流子迁移率的应力施加到与栅电极的一部分的沟道区。

公开(公告)号：US20060017070A1

公开(公告)日：2006-01-26

申请号：US11148208

申请日：2005-06-09

Applicant: Daisaku Ikoma ,  Atsuhiro Kajiya ,  Katsuhiro Ootani ,  Kyoji Yamashita

Inventor： Daisaku Ikoma ,  Atsuhiro Kajiya ,  Katsuhiro Ootani ,  Kyoji Yamashita

IPC: H01L29/76

CPC classification number: H01L21/76895 ,  H01L21/823475 ,  H01L27/0207

Abstract: A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.

Abstract translation: 半导体器件包括半导体衬底; 扩散区，其形成在半导体衬底中并用作用于形成MIS晶体管的区域; 围绕扩散区域的元件隔离区域; 形成在扩散区域和元件隔离区域两侧的至少一个栅极导体膜包括位于扩散区域上的栅极电极部分和位于元件隔离区域上的栅极互连部件，并且栅极长度具有恒定的尺寸 方向; 以及覆盖所述栅电极的层间绝缘膜。 半导体器件还包括通过层间绝缘膜的栅极接触，连接到栅极互连部分，并且具有大于栅极互连部分的栅极长度方向的尺寸。

公开(公告)号：US20070007603A1

公开(公告)日：2007-01-11

申请号：US11481909

申请日：2006-07-07

Applicant: Takayuki Yamada ,  Atsuhiro Kajiya ,  Satoshi Ishikura

Inventor： Takayuki Yamada ,  Atsuhiro Kajiya ,  Satoshi Ishikura

IPC: H01L29/76

CPC classification number: H01L27/11 ,  H01L27/0203 ,  Y10S257/903

Abstract: A first semiconductor region has a smaller width along a gate length direction than a second semiconductor region. In this case, the first semiconductor region has a larger width along a gate width direction than the second semiconductor region.

Abstract translation: 第一半导体区域沿栅极长度方向具有比第二半导体区域更小的宽度。 在这种情况下，第一半导体区域沿栅极宽度方向的宽度比第二半导体区域宽。

公开(公告)号：US20050193013A1

公开(公告)日：2005-09-01

申请号：US10991457

申请日：2004-11-19

Applicant: Kyoji Yamashita ,  Katsuhiro Ohtani ,  Atsuhiro Kajiya

Inventor： Kyoji Yamashita ,  Katsuhiro Ohtani ,  Atsuhiro Kajiya

IPC: H01L29/00 ,  G06F7/00 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC classification number: G01R31/2648 ,  H01L22/14

Abstract: A first relational expression representing a relationship among gate bias Vd, carrier mobility μ, electric effective channel length Leff and transconductance Gm, and a second relational expression representing a relationship among maximum-transconductance ratio Gmmax L=Lref/Gmmax L=Ltar between a target transistor and a reference transistor and electric effective channel lengths Leff and Lref of the respective transistors are used. Maximum transconductance Gmmax obtained when gate bias Vd is changed is determined and electric effective channel length Leff is estimated by substituting the value of maximum transconductance Gmmax in the second relational expression. The correlation between 1/Gmmax and Lgsem is strong enough to allow maximum transconductance Gmmax to be used in monitoring a process variation of a physical gate length.

Abstract translation: 表示栅极偏置V SUB，载流子迁移率μ，电有效沟道长度L eff和跨导G m之间的关系的第一关系表达式，以及 表示目标晶体管和参考晶体管之间的最大跨导比G max max L = L ref / N maxax L = 使用各个晶体管的L eff和L ref ref。 确定当栅极偏压V Sub1变化时获得的最大跨导G ，并且通过将最大值的值代入最大值来估计有效通道长度L eff 第二关系表达式中的跨导G mmax 。 1 / G 和/或L> gsem 之间的相关性足够强，以允许最大跨导G max max用于监测 物理门长度。

公开(公告)号：US5396096A

公开(公告)日：1995-03-07

申请号：US132323

申请日：1993-10-06

Applicant: Susumu Akamatsu ,  Atsuhiro Kajiya

Inventor： Susumu Akamatsu ,  Atsuhiro Kajiya

IPC: H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L21/823807 ,  H01L21/76218 ,  H01L27/0928

Abstract: In a semiconductor device, a FET and an isolation are provided on a semiconductor substrate and a channel stop region is provided under the isolation. At least a region to which a high voltage is applied of a source region and a drain region of the FET is separated from the channel stop region, and a first buffer region doped with an impurity for adjusting the threshold level is provided therebetween. A region under a gate electrode and adjacent to the isolation serves as a second buffer region to which an impurity for adjusting the threshold level is doped. With the first buffer region, a depletion region at a boundary of the drain region and the channel stop region is ensured, obtaining a superior durability to high voltage of the source/drain region. With the second buffer region, leakage current between the source region and the drain region is prevented.

Abstract translation: 在半导体装置中，在半导体基板上设置FET和隔离，在隔离下设置沟道停止区域。 至少一个施加FET的源极区域和漏极区域的高电压的区域与沟道停止区域分离，并且在其间提供掺杂有用于调节阈值电平的杂质的第一缓冲区域。 在栅电极下方并且与隔离相邻的区域用作掺杂用于调整阈值电平的杂质的第二缓冲区域。 利用第一缓冲区域，确保漏极区域和沟道停止区域的边界处的耗尽区域，从而获得对源极/漏极区域的高电压的优异的耐久性。 利用第二缓冲区域，防止源极区域和漏极区域之间的漏电流。

公开(公告)号：US20060170065A1

公开(公告)日：2006-08-03

申请号：US11258931

申请日：2005-10-27

Applicant: Kentaro Nakanishi ,  Isao Miyanaga ,  Atsuhiro Kajiya

Inventor： Kentaro Nakanishi ,  Isao Miyanaga ,  Atsuhiro Kajiya

IPC: H01L29/94

CPC classification number: H01L21/823462 ,  H01L21/823456

Abstract: In a semiconductor device according to the present invention, the power source voltage Vdd1 of a core transistor Tr1, the power source voltage Vdd2 of an I/O transistor Tr2, and the power source voltage Vdd3 of an I/O transistor Tr3 satisfy Vdd1

Abstract translation: 在根据本发明的半导体器件中，芯晶体管Tr 1的电源电压Vdd 1，I / O晶体管Tr 2的电源电压Vdd 2和I / O的电源电压Vdd 3 晶体管Tr 3满足Vdd 1