Invention Application
- Patent Title: Method for evaluating semiconductor device
- Patent Title (中): 半导体器件评估方法
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Application No.: US10991457Application Date: 2004-11-19
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Publication No.: US20050193013A1Publication Date: 2005-09-01
- Inventor: Kyoji Yamashita , Katsuhiro Ohtani , Atsuhiro Kajiya
- Applicant: Kyoji Yamashita , Katsuhiro Ohtani , Atsuhiro Kajiya
- Assignee: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Current Assignee: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Priority: JP2004-038898 20040216
- Main IPC: H01L29/00
- IPC: H01L29/00 ; G06F7/00 ; H01L21/336 ; H01L21/8234 ; H01L27/088 ; H01L29/78

Abstract:
A first relational expression representing a relationship among gate bias Vd, carrier mobility μ, electric effective channel length Leff and transconductance Gm, and a second relational expression representing a relationship among maximum-transconductance ratio Gmmax L=Lref/Gmmax L=Ltar between a target transistor and a reference transistor and electric effective channel lengths Leff and Lref of the respective transistors are used. Maximum transconductance Gmmax obtained when gate bias Vd is changed is determined and electric effective channel length Leff is estimated by substituting the value of maximum transconductance Gmmax in the second relational expression. The correlation between 1/Gmmax and Lgsem is strong enough to allow maximum transconductance Gmmax to be used in monitoring a process variation of a physical gate length.
Information query
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