公开(公告)号：US5644159A

公开(公告)日：1997-07-01

申请号：US613939

申请日：1996-03-13

Applicant: Masao Arimoto

Inventor： Masao Arimoto

IPC: H01L27/04 ,  G05F3/30 ,  H01L21/822 ,  H01L27/06 ,  H01L27/082 ,  H01L27/10

CPC classification number: H01L27/0623 ,  G05F3/30 ,  H01L27/082 ,  Y10S257/919

Abstract: A semiconductor device implemented using a transistor (Q1) including at least one emitter (E1) and a transistor (Q2) which is larger than the transistor (Q1) including n emitters (E21 to E2n) each having the same area as the emitter (E1) of the transistor (Q1). The emitter (E1) of the transistor (Q1) is disposed between the emitters (E21 to E2n) of the transistor (Q2). When there is deflection of a substrate due to a stress to cause distortion in shape of the emitters, the emitter (E1) has much less distortion in shape than the emitters located on the end portions of the row region in the longitudinal direction. Since the transistor (Q2) has a number of emitters, the distortion in shape of the emitters (E21 to E2n) of the transistor (Q2), if any, has little effect on the whole.

Abstract translation: 一种使用包括至少一个发射极（E1）和晶体管（Q2）的晶体管（Q1）的半导体器件，该晶体管（Q1）和晶体管（Q1）大于包括与发射极相同的面积的n个发射极（E21〜E2n） E1）。 晶体管（Q1）的发射极（E1）配置在晶体管（Q2）的发射极（E21〜E2n）之间。 当由于应力引起的基板由于发射体的形状发生变形而发生偏转时，发射极（E1）的形状畸变比位于行区域的纵向方向的端部上的发射体的形状小得多。 由于晶体管（Q2）具有多个发射极，因此晶体管（Q2）的发射极（E21〜E2n）的形状变形（总之）几乎没有影响。

公开(公告)号：US5363070A

公开(公告)日：1994-11-08

申请号：US162900

申请日：1993-12-08

Applicant: Masao Arimoto

Inventor： Masao Arimoto

IPC: H03H7/24 ,  H03H7/48

CPC classification number: H03H7/24

Abstract: An attenuator includes first resistors that are connected in series to each other at connection nodes and between an input node and a fixed voltage node, voltage output nodes coupled to the input node and the respective connection nodes of the first resistors, switches and corresponding second resistors being respectively connected in series between the connection nodes and voltage output nodes and commonly connected to an output node, and a load capacitance connected between an output node and the fixed voltage node. The phase between input and output signals is independent of the attenuation. A phase difference is added by the second resistor so that the phase shift determined by the voltage dividing ratio of the first resistors selected by closing a switch and by the value of the load capacitance is compensated.

Abstract translation: 衰减器包括在连接节点处和输入节点与固定电压节点之间彼此串联连接的第一电阻器，耦合到输入节点的电压输出节点和第一电阻器，开关和对应的第二电阻器的相应连接节点 分别连接在连接节点和电压输出节点之间，并且共同连接到输出节点，以及连接在输出节点和固定电压节点之间的负载电容。 输入和输出信号之间的相位与衰减无关。 通过第二电阻器相加相位差，从而补偿由闭合开关所选择的第一电阻器的分压比和负载电容值所决定的相移。

公开(公告)号：US5334950A

公开(公告)日：1994-08-02

申请号：US018537

申请日：1993-02-17

Applicant: Masao Arimoto

Inventor： Masao Arimoto

IPC: H03F3/18 ,  H03F3/30

CPC classification number: H03F3/3001

Abstract: The gate of a first source-grounded transistor and the input of a buffer circuit are directly connected to an input terminal of a class-AB push-pull circuit. An input signal directly drives the first source-grounded transistor and is transmitted through the buffer circuit to a voltage-to-current converter and converted into a current signal. On receipt of the current signal, an inverting amplifier develops a voltage of reversed polarity which is applied to the gate of a second source-grounded transistor to drive the second transistor. The drains of the first and second transistors are connected to each other and their connecting point serves as an output terminal of the circuit. A class-AB push-pull drive circuit having such an arrangement requires a significantly reduced input signal voltage and a reduced power supply voltage.

Abstract translation: 第一源极接地晶体管的栅极和缓冲电路的输入直接连接到AB类推挽电路的输入端。 输入信号直接驱动第一源极接地晶体管，并通过缓冲电路传输到电压 - 电流转换器并转换为电流信号。 在接收到当前信号时，反相放大器产生反向极性的电压，该电压施加到第二源极接地晶体管的栅极以驱动第二晶体管。 第一和第二晶体管的漏极相互连接，它们的连接点用作电路的输出端。 具有这种布置的AB类推挽驱动电路需要显着降低的输入信号电压和降低的电源电压。

公开(公告)号：US5523613A

公开(公告)日：1996-06-04

申请号：US383840

申请日：1995-02-06

Applicant: Masao Arimoto

Inventor： Masao Arimoto

IPC: H01L27/04 ,  G05F3/30 ,  H01L21/822 ,  H01L27/06 ,  H01L27/082 ,  H01L27/10

CPC classification number: H01L27/0623 ,  G05F3/30 ,  H01L27/082 ,  Y10S257/919

Abstract: A semiconductor device implemented using a transistor (Q1) including at least one emitter (E1) and a transistor (Q2) which is larger than the transistor (Q1) including n emitters (E21 to E2n) each having the same area as the emitter (E1) of the transistor (Q1). The emitter (E1) of the transistor (Q1) is disposed between the emitters (E21 to E2n) of the transistor (Q2). When there is deflection of a substrate due to a stress to cause distortion in shape of the emitters, the emitter (E1) has much less distortion in shape than the emitters located on the end portions of the row region in the longitudinal direction. Since the transistor (Q2) has a number of emitters, the distortion in shape of the emitters (E21 to E2n) of the transistor (Q2), if any, has little effect on the whole.

Abstract translation: 一种使用包括至少一个发射极（E1）和晶体管（Q2）的晶体管（Q1）的半导体器件，该晶体管（Q1）和晶体管（Q1）大于包括与发射极相同的面积的n个发射极（E21〜E2n） E1）。 晶体管（Q1）的发射极（E1）配置在晶体管（Q2）的发射极（E21〜E2n）之间。 当由于应力引起的基板由于发射体的形状发生变形而发生偏转时，发射极（E1）的形状畸变比位于行区域的纵向方向的端部上的发射体的形状小得多。 由于晶体管（Q2）具有多个发射极，因此晶体管（Q2）的发射极（E21〜E2n）的形状变形（总之）几乎没有影响。

公开(公告)号：US5394146A

公开(公告)日：1995-02-28

申请号：US69109

申请日：1993-05-28

Applicant: Masao Arimoto

Inventor： Masao Arimoto

IPC: H03M1/10 ,  H03M1/66 ,  H03M1/68 ,  H03M1/06

CPC classification number: H03M1/662

Abstract: A D-A converter in which a phase deviation in load current is inhibited and a digital to analog conversion accuracy is enhanced. A data dividing block (7) is provided to switch a path depending upon a value of the most significant bit of an N bit digital signal (DATA) so as to conduct the D-A converting and the V-I converting based upon an (N-1)bit digital signal (DATA(N-1)) in either one of a first analog current output path consisting of a D-A converting block (11) and a V-I converting unit (210) and a second analog current output path consisting of a D-A converting block (12) and a V-I converting unit (220). Thus, since a large range of load current can be obtained and a phase deviation in the load current can be inhibited, a D-A conversion accuracy is enhanced.

Abstract translation: 一种D-A转换器，其中禁止负载电流的相位偏差并提高数模转换精度。 数据分割块（7）被提供以根据N位数字信号（DATA）的最高有效位的值来切换路径，以便基于（N-1）数据信号进行DA转换和VI转换， 在由DA转换块（VI）和VI转换单元（210）组成的第一模拟电流输出路径和由DA转换单元（210）组成的第二模拟电流输出路径中的任何一个中的位数字信号（DATA（N-1） 块（12）和VI转换单元（220）。 因此，由于可以获得大范围的负载电流并且可以抑制负载电流的相位偏差，因此D-A转换精度提高。

公开(公告)号：US5148120A

公开(公告)日：1992-09-15

申请号：US717060

申请日：1991-06-18

Applicant: Kenji Kano ,  Yusuke Yamada ,  Masao Arimoto ,  Shoji Uehata

Inventor： Kenji Kano ,  Yusuke Yamada ,  Masao Arimoto ,  Shoji Uehata

IPC: H03F3/30

CPC classification number: H03F3/3001

Abstract: A class-AB push-pull drive circuit comprises a P channel MOS transistor having a source connected with a DC power source, a drain connected with an output terminal and a control electrode coupled with an input terminal through a voltage-to-current converter and a current-to-voltage converter and an N channel MOS transistor having a source grounded, a drain connected with the output terminal and a control electrode coupled with the input terminal. Conversion characteristics of the converters are so set that a potential difference between the control electrodes of the transistors is kept constant independently of the voltage of an input signal. Thus, the rise and fall of voltage at the output terminal during the conducting state of respective transistors is decreased. In addition, a push-pull drive operation by the transistors can be achieved in accordance with the input signal.

Abstract translation: AB类推挽驱动电路包括具有与DC电源连接的源极的P沟道MOS晶体管，与输出端子连接的漏极和通过电压 - 电流转换器与输入端子耦合的控制电极， 电流 - 电压转换器和源极接地的N沟道MOS晶体管，与输出端连接的漏极和与输入端耦合的控制电极。 转换器的转换特性被设定为使得晶体管的控制电极之间的电位差保持恒定，而与输入信号的电压无关。 因此，在各个晶体管的导通状态期间输出端子处的电压的上升和下降降低。 此外，可以根据输入信号实现晶体管的推挽驱动操作。