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    DIELECTRIC-BASED MEMORY CELLS HAVING MULTI-LEVEL ONE-TIME PROGRAMMABLE AND BI-LEVEL REWRITEABLE OPERATING MODES AND METHODS OF FORMING THE SAME
    3.
    发明申请
    DIELECTRIC-BASED MEMORY CELLS HAVING MULTI-LEVEL ONE-TIME PROGRAMMABLE AND BI-LEVEL REWRITEABLE OPERATING MODES AND METHODS OF FORMING THE SAME 有权
    具有多级一次可编程和双层可操作操作模式的基于介质的存储器单元及其形成方法

    公开(公告)号：US20150325310A1

    公开(公告)日：2015-11-12

    申请号：US14804126

    申请日：2015-07-20

    Applicant: SanDisk 3D LLC

    Inventor： Abhijit Bandyopadhyay ,  Tanmay Kumar ,  Scott Brad Herner ,  Christopher J. Petti ,  Roy E. Scheuerlein

    IPC: G11C17/16 ,  G11C17/18 ,  G11C11/56

    CPC classification number: G11C17/165 ,  G11C11/5692 ,  G11C17/18 ,  H01L27/1021 ,  H01L27/11206 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2481 ,  H01L29/8615 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

    Abstract: A method of programming a memory cell is provided. The memory cell includes a memory element having a first conductive material layer, a first dielectric material layer above the first conductive material layer, a second conductive material layer above the first dielectric material layer, a second dielectric material layer above the second conductive material layer, and a third conductive material layer above the second dielectric material layer. One or both of the first and second conductive material layers comprises a stack of a metal material layer and a highly doped semiconductor material layer. The memory cell has a first memory state upon fabrication corresponding to a first read current. The method includes applying a first programming pulse to the memory cell with a first current limit. The first programming pulse programs the memory cell to a second memory state that corresponds to a second read current greater than the first read current.

    Abstract translation: 提供了一种编程存储器单元的方法。 存储单元包括具有第一导电材料层，在第一导电材料层上方的第一介电材料层，第一介电材料层上方的第二导电材料层，第二导电材料层上方的第二介电材料层的存储元件， 以及在第二介电材料层上方的第三导电材料层。 第一和第二导电材料层中的一个或两个包括金属材料层和高掺杂半导体材料层的叠层。 存储单元在制造时具有对应于第一读取电流的第一存储器状态。 该方法包括以第一电流限制对存储器单元施加第一编程脉冲。 第一编程脉冲将存储器单元编程为对应于大于第一读取电流的第二读取电流的第二存储器状态。

    METHODS AND APPARATUS FOR LAYOUT OF THREE DIMENSIONAL MATRIX ARRAY MEMORY FOR REDUCED COST PATTERNING
    4.
    发明申请
    METHODS AND APPARATUS FOR LAYOUT OF THREE DIMENSIONAL MATRIX ARRAY MEMORY FOR REDUCED COST PATTERNING 有权
    用于降低成本花纹的三维矩阵阵列存储器的布局方法和装置

    公开(公告)号：US20140328105A1

    公开(公告)日：2014-11-06

    申请号：US14334653

    申请日：2014-07-17

    Applicant: SanDisk 3D LLC

    Inventor： Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

    IPC: G11C5/06

    CPC classification number: G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

    Abstract: Apparatus, methods, and systems are provided for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled thereto; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks, are formed using a sidewall defined process, and have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern that allows a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Other aspects are disclosed.

    Abstract translation: 为三维存储器的存储器层布局提供了装置，方法和系统。 存储层包括多个存储器阵列块; 耦合到其上的多个存储线; 以及用于将存储器层耦合到三维存储器中的其它存储器层的多个zia接触区域。 存储器线从存储器阵列块延伸，使用侧壁限定的工艺形成，并且半间距尺寸小于形成存储器线的光刻工具的标称最小特征尺寸能力。 zia接触区域的尺寸约为存储器线的半间距尺寸的四倍。 存储线被布置成允许单个存储器线与单个zia接触区域相交并且为其它zia接触区域提供在其它存储器线路之间的区域的图案。 公开其他方面。

    Method for reducing dielectric overetch when making contact to conductive features
    5.
    发明授权
    Method for reducing dielectric overetch when making contact to conductive features 有权
    在与导电特征接触时减小介质过蚀刻的方法

    公开(公告)号：US08741768B2

    公开(公告)日：2014-06-03

    申请号：US13938975

    申请日：2013-07-10

    Applicant: SanDisk 3D LLC

    Inventor： Christopher J. Petti

    IPC: H01L21/311

    CPC classification number: H01L21/768 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76829 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method is provided that includes forming conductive or semiconductive features above a first dielectric material, depositing a second dielectric material above the conductive or semiconductive features, etching a void in the second dielectric material, wherein the etch stops on the first dielectric material, and exposing a portion of the conductive or semiconductive features. Numerous other aspects are provided.

    Abstract translation: 提供了一种方法，其包括在第一电介质材料之上形成导电或半导体特征，在导电或半导体特征之上沉积第二电介质材料，蚀刻第二电介质材料中的空隙，其中蚀刻停止在第一电介质材料上， 导电或半导体特征的一部分。 提供了许多其他方面。

    VERTICAL 1T-1R MEMORY CELLS, MEMORY ARRAYS AND METHODS OF FORMING THE SAME
    8.
    发明申请
    VERTICAL 1T-1R MEMORY CELLS, MEMORY ARRAYS AND METHODS OF FORMING THE SAME 有权
    垂直1T-1R记忆细胞，记忆阵列及其形成方法

    公开(公告)号：US20150131360A1

    公开(公告)日：2015-05-14

    申请号：US14075010

    申请日：2013-11-08

    Applicant: SanDisk 3D LLC

    Inventor： Christopher J. Petti

    IPC: H01L27/24 ,  H01L45/00 ,  H01L21/8234 ,  G11C13/00

    CPC classification number: H01L27/2481 ,  G11C13/0002 ,  H01L21/823487 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1675

    Abstract: Vertical 1T-1R memory cells, memory arrays of vertical 1T-1R memory calls, and methods of forming such memory cells and memory arrays are described. The memory cells each include a vertical transistor and a resistivity-switching element coupled in series with and disposed above or below the vertical transistor. The vertical transistor includes a controlling electrode coupled to a word line that is above or below the vertical transistor. The controlling electrode is disposed on a sidewall of the vertical transistor. Each vertical transistor includes a first terminal coupled to a bit line, a second terminal comprising the controlling electrode coupled to a word line, and a third terminal coupled to the resistivity-switching element.

    Abstract translation: 描述垂直1T-1R存储器单元，垂直1T-1R存储器调用的存储器阵列，以及形成这种存储器单元和存储器阵列的方法。 每个存储单元都包括垂直晶体管和与垂直晶体管串联连接并设置在垂直晶体管上方或下方的电阻率开关元件。 垂直晶体管包括耦合到位于垂直晶体管之上或之下的字线的控制电极。 控制电极设置在垂直晶体管的侧壁上。 每个垂直晶体管包括耦合到位线的第一端子，包括耦合到字线的控制电极的第二端子和耦合到电阻率开关元件的第三端子。

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