Vertical 1T-1R memory cells, memory arrays of vertical 1T-1R memory calls, and methods of forming such memory cells and memory arrays are described. The memory cells each include a vertical transistor and a resistivity-switching element coupled in series with and disposed above or below the vertical transistor. The vertical transistor includes a controlling electrode coupled to a word line that is above or below the vertical transistor. The controlling electrode is disposed on a sidewall of the vertical transistor. Each vertical transistor includes a first terminal coupled to a bit line, a second terminal comprising the controlling electrode coupled to a word line, and a third terminal coupled to the resistivity-switching element.