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    DIELECTRIC-BASED MEMORY CELLS HAVING MULTI-LEVEL ONE-TIME PROGRAMMABLE AND BI-LEVEL REWRITEABLE OPERATING MODES AND METHODS OF FORMING THE SAME
    1.
    发明申请
    DIELECTRIC-BASED MEMORY CELLS HAVING MULTI-LEVEL ONE-TIME PROGRAMMABLE AND BI-LEVEL REWRITEABLE OPERATING MODES AND METHODS OF FORMING THE SAME 有权
    具有多级一次可编程和双层可操作操作模式的基于介质的存储器单元及其形成方法

    公开(公告)号：US20150325310A1

    公开(公告)日：2015-11-12

    申请号：US14804126

    申请日：2015-07-20

    Applicant: SanDisk 3D LLC

    Inventor： Abhijit Bandyopadhyay ,  Tanmay Kumar ,  Scott Brad Herner ,  Christopher J. Petti ,  Roy E. Scheuerlein

    IPC: G11C17/16 ,  G11C17/18 ,  G11C11/56

    CPC classification number: G11C17/165 ,  G11C11/5692 ,  G11C17/18 ,  H01L27/1021 ,  H01L27/11206 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2481 ,  H01L29/8615 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

    Abstract: A method of programming a memory cell is provided. The memory cell includes a memory element having a first conductive material layer, a first dielectric material layer above the first conductive material layer, a second conductive material layer above the first dielectric material layer, a second dielectric material layer above the second conductive material layer, and a third conductive material layer above the second dielectric material layer. One or both of the first and second conductive material layers comprises a stack of a metal material layer and a highly doped semiconductor material layer. The memory cell has a first memory state upon fabrication corresponding to a first read current. The method includes applying a first programming pulse to the memory cell with a first current limit. The first programming pulse programs the memory cell to a second memory state that corresponds to a second read current greater than the first read current.

    Abstract translation: 提供了一种编程存储器单元的方法。 存储单元包括具有第一导电材料层，在第一导电材料层上方的第一介电材料层，第一介电材料层上方的第二导电材料层，第二导电材料层上方的第二介电材料层的存储元件， 以及在第二介电材料层上方的第三导电材料层。 第一和第二导电材料层中的一个或两个包括金属材料层和高掺杂半导体材料层的叠层。 存储单元在制造时具有对应于第一读取电流的第一存储器状态。 该方法包括以第一电流限制对存储器单元施加第一编程脉冲。 第一编程脉冲将存储器单元编程为对应于大于第一读取电流的第二读取电流的第二存储器状态。

    MIIIM DIODE HAVING LANTHANUM OXIDE
    7.
    发明申请
    MIIIM DIODE HAVING LANTHANUM OXIDE 审中-公开
    具有氧化铝的MIIIM二极管

    公开(公告)号：US20130181181A1

    公开(公告)日：2013-07-18

    申请号：US13787505

    申请日：2013-03-06

    Applicant: SanDisk 3D LLC

    Inventor： Deepak C. Sekar ,  Tanmay Kumar ,  Peter Rabkin ,  Xiying Chen Costa

    IPC: H01L45/00

    CPC classification number: H01L45/145 ,  H01L27/2418 ,  H01L45/00 ,  H01L45/04 ,  H01L45/06 ,  H01L45/144 ,  H01L45/149

    Abstract: A MIIIM diode and method of fabricating are disclosed. In one aspect, the MIIIM diode comprises a first metal electrode, a first region comprising a first insulator material having an interface with the first metal electrode, a second region comprising a second insulator material having an interface with the first insulator material, a third region comprising a third insulator material having an interface with the second insulator material, and a second metal electrode having an interface with the third insulator material. At least one of the first, second, or third insulator materials is lanthanum oxide.

    Abstract translation: 公开了一种MIIIM二极管及其制造方法。 一方面，MIIIM二极管包括第一金属电极，第一区域，包括与第一金属电极具有界面的第一绝缘体材料，第二区域包括与第一绝缘体材料具有界面的第二绝缘体材料，第三区域 包括具有与第二绝缘体材料的界面的第三绝缘体材料和与第三绝缘体材料具有界面的第二金属电极。 第一，第二或第三绝缘体材料中的至少一种是氧化镧。

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