公开(公告)号：US20160126292A1

公开(公告)日：2016-05-05

申请号：US14529624

申请日：2014-10-31

Applicant: SANDISK 3D LLC

Inventor： Naohito Yanagida ,  Cheng Feng ,  Michiaki Sano ,  Akira Nakada ,  Steven J. Radigan ,  Eiji Hayashi

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L45/141 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1273 ,  H01L45/145 ,  H01L45/1616

Abstract: An alternating stack of electrically conductive layers and electrically insulating layers is formed over global bit lines formed on a substrate. The alternating stack is patterned to form a line stack of electrically conductive lines and electrically insulating lines. Trench isolation structures are formed within each trench to define a plurality of memory openings laterally spaced from one another by the line stack in one direction and by trench isolation structures in another direction. The electrically conductive lines are laterally recessed relative to sidewall surfaces of the electrically insulating lines. A read/write memory material is deposited in recesses, and is anisotropically etched so that a top surface of a global bit line is physically exposed at a bottom of each memory opening. An electrically conductive bit line is formed within each memory opening to form a resistive random access memory device.

公开(公告)号：US08658526B2

公开(公告)日：2014-02-25

申请号：US13760877

申请日：2013-02-06

Applicant: SanDisk 3D LLC

Inventor： Huiwen Xu ,  Yung-Tin Chen ,  Steven J. Radigan

IPC: H01L21/44

CPC classification number: H01L21/3088 ,  H01L21/0337 ,  H01L21/0338 ,  H01L27/101 ,  H01L27/1021

Abstract: A method is provided that includes forming completely distinct first features above a substrate, forming sidewall spacers on the first features, filling spaces between adjacent sidewall spacers with filler features, and removing the sidewall spacers. Numerous other aspects are provided.

Abstract translation: 提供了一种方法，其包括在基底上形成完全不同的第一特征，在第一特征上形成侧壁间隔物，在填充物特征之间填充相邻侧壁间隔物之间​​的空间，以及去除侧壁间隔物。 提供了许多其他方面。

公开(公告)号：US08637389B2

公开(公告)日：2014-01-28

申请号：US13744971

申请日：2013-01-18

Applicant: SanDisk 3D LLC

Inventor： Yung-Tin Chen ,  Steven J. Radigan

IPC: H01L21/3205

CPC classification number: H01L45/1691 ,  H01L21/0337 ,  H01L21/0338 ,  H01L27/1021

Abstract: A method of making a memory array is provided that includes forming a layer over a substrate, forming features over the layer, forming sidewall spacers on each of the features, filling spaces between adjacent sidewall spacers with filler features, removing the sidewall spacers to leave the features and the filler features, and etching the layer using the features and the filler features as a mask to form pillar shaped nonvolatile memory cells. Numerous other aspects are provided.

Abstract translation: 提供了一种制造存储器阵列的方法，其包括在衬底上形成层，在层上形成特征，在每个特征上形成侧壁间隔物，在填充物特征之间填充相邻侧壁间隔物之间​​的空间，去除侧壁间隔物， 特征和填料特征，并且使用特征和填料特征作为掩模来蚀刻层以形成柱状非易失性存储单元。 提供了许多其他方面。

公开(公告)号：US20130130467A1

公开(公告)日：2013-05-23

申请号：US13744971

申请日：2013-01-18

Applicant: SANDISK 3D LLC

Inventor： Yung-Tin Chen ,  Steven J. Radigan

IPC: H01L45/00

CPC classification number: H01L45/1691 ,  H01L21/0337 ,  H01L21/0338 ,  H01L27/1021

Abstract: A method of making a memory array is provided that includes forming a layer over a substrate, forming features over the layer, forming sidewall spacers on each of the features, filling spaces between adjacent sidewall spacers with filler features, removing the sidewall spacers to leave the features and the filler features, and etching the layer using the features and the filler features as a mask to form pillar shaped nonvolatile memory cells. Numerous other aspects are provided.

Abstract translation: 提供了一种制造存储器阵列的方法，其包括在衬底上形成层，在层上形成特征，在每个特征上形成侧壁间隔物，在填充物特征之间填充相邻侧壁间隔物之间​​的空间，去除侧壁间隔物， 特征和填料特征，并且使用特征和填料特征作为掩模来蚀刻层以形成柱状非易失性存储单元。 提供了许多其他方面。

公开(公告)号：US20130244395A1

公开(公告)日：2013-09-19

申请号：US13890321

申请日：2013-05-09

Applicant: SANDISK 3D LLC

Inventor： Steven J. Radigan ,  Usha Raghuram ,  Samuel V. Dunton ,  Michael W. Konevecki

IPC: H01L29/66

CPC classification number: H01L23/5252 ,  H01L27/1021 ,  H01L29/6609 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided for forming a monolithic three dimensional memory array. The method includes forming a first memory level above a substrate, and monolithically forming a second memory level above the first memory level. The first memory level is formed by forming first substantially parallel conductors extending in a first direction, forming first pillars above the first conductors, each first pillar including a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, depositing a first dielectric layer above the first pillars, etching first trenches in the first dielectric layer, the first trenches extending in a second direction. After etching, a lowest point in the trenches is above a lowest point of the first conductive layer or layerstack, and the first conductive layer or layerstack does not include a resistivity-switching metal oxide or nitride. Numerous other aspects are provided.

Abstract translation: 提供了一种用于形成单片三维存储器阵列的方法。 该方法包括在衬底上形成第一存储器级，并且在第一存储器级上方单片地形成第二存储器级。 第一存储器级通过形成沿第一方向延伸的第一基本上平行的导体形成，在第一导体上方形成第一柱，每个第一柱包括在垂直取向的二极管上方的第一导电层或层堆叠，第一柱形成于单个光刻 步骤，在第一柱上方沉积第一介电层，蚀刻第一介电层中的第一沟槽，第一沟槽沿第二方向延伸。 在蚀刻之后，沟槽中的最低点高于第一导电层或层堆叠的最低点，并且第一导电层或层堆叠不包括电阻率切换金属氧化物或氮化物。 提供了许多其他方面。

公开(公告)号：US09666799B2

公开(公告)日：2017-05-30

申请号：US14529624

申请日：2014-10-31

Applicant: SANDISK 3D LLC

Inventor： Naohito Yanagida ,  Cheng Feng ,  Michiaki Sano ,  Akira Nakada ,  Steven J. Radigan ,  Eiji Hayashi

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/141 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1273 ,  H01L45/145 ,  H01L45/1616

Abstract: An alternating stack of electrically conductive layers and electrically insulating layers is formed over global bit lines formed on a substrate. The alternating stack is patterned to form a line stack of electrically conductive lines and electrically insulating lines. Trench isolation structures are formed within each trench to define a plurality of memory openings laterally spaced from one another by the line stack in one direction and by trench isolation structures in another direction. The electrically conductive lines are laterally recessed relative to sidewall surfaces of the electrically insulating lines. A read/write memory material is deposited in recesses, and is anisotropically etched so that a top surface of a global bit line is physically exposed at a bottom of each memory opening. An electrically conductive bit line is formed within each memory opening to form a resistive random access memory device.

公开(公告)号：US20130183829A1

公开(公告)日：2013-07-18

申请号：US13760877

申请日：2013-02-06

Applicant: SANDISK 3D LLC

Inventor： Huiwen Xu ,  Yung-Tin Chen ,  Steven J. Radigan

IPC: H01L21/308

CPC classification number: H01L21/3088 ,  H01L21/0337 ,  H01L21/0338 ,  H01L27/101 ,  H01L27/1021

Abstract: A method is provided that includes forming completely distinct first features above a substrate, forming sidewall spacers on the first features, filling spaces between adjacent sidewall spacers with filler features, and removing the sidewall spacers. Numerous other aspects are provided.

Abstract translation: 提供了一种方法，其包括在基底上形成完全不同的第一特征，在第一特征上形成侧壁间隔物，在填充物特征之间填充相邻侧壁间隔物之间​​的空间，以及去除侧壁间隔物。 提供了许多其他方面。

公开(公告)号：US08722518B2

公开(公告)日：2014-05-13

申请号：US13890321

申请日：2013-05-09

Applicant: SanDisk 3D LLC

Inventor： Steven J. Radigan ,  Usha Raghuram ,  Samuel V. Dunton ,  Michael W. Konevecki

IPC: H01L21/326 ,  H01L21/82 ,  H01L21/44 ,  H01L23/525 ,  H01L27/102 ,  H01L29/66

CPC classification number: H01L23/5252 ,  H01L27/1021 ,  H01L29/6609 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided for forming a monolithic three dimensional memory array. The method includes forming a first memory level above a substrate, and monolithically forming a second memory level above the first memory level. The first memory level is formed by forming first substantially parallel conductors extending in a first direction, forming first pillars above the first conductors, each first pillar including a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, depositing a first dielectric layer above the first pillars, etching first trenches in the first dielectric layer, the first trenches extending in a second direction. After etching, a lowest point in the trenches is above a lowest point of the first conductive layer or layerstack, and the first conductive layer or layerstack does not include a resistivity-switching metal oxide or nitride. Numerous other aspects are provided.

Abstract translation: 提供了一种用于形成单片三维存储器阵列的方法。 该方法包括在衬底上形成第一存储器级，并且在第一存储器级上方单片地形成第二存储器级。 第一存储器级通过形成沿第一方向延伸的第一基本上平行的导体形成，在第一导体上方形成第一柱，每个第一柱包括在垂直取向的二极管上方的第一导电层或层堆叠，第一柱形成于单个光刻 步骤，在第一柱上方沉积第一介电层，蚀刻第一介电层中的第一沟槽，第一沟槽沿第二方向延伸。 在蚀刻之后，沟槽中的最低点高于第一导电层或层堆叠的最低点，并且第一导电层或层堆叠不包括电阻率切换金属氧化物或氮化物。 提供了许多其他方面。

公开(公告)号：US20130336037A1

公开(公告)日：2013-12-19

申请号：US13838782

申请日：2013-03-15

Applicant: SANDISK 3D LLC

Inventor： Yung-Tin Chen ,  Steven J. Radigan ,  Roy E. Scheuerlein ,  Raul Adrian Cernea

IPC: G11C5/06 ,  H01L27/105

CPC classification number: H01L27/249 ,  G06F12/0238 ,  G11C5/025 ,  G11C5/06 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2213/71 ,  H01L21/76877 ,  H01L27/1052 ,  H01L27/2454 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

Abstract: A vertical switching layer of a 3D memory device serves to switch a set of vertical local bit lines to a corresponding set of global bit lines, the vertical switching layer being a 2D array of TFT channels of vertical thin-film transistors (TFTs) aligned to connect to an array of local bit lines, each TFT switching a local bit line to a corresponding global bit line. The TFTs in the array have a separation of lengths Lx and Ly along the x- and y-axis respectively such that a gate material layer forms a surround gate around each TFT in an x-y plane and has a thickness that merges to form a row select line along the x-axis while maintaining a separation of length Ls between individual row select lines. The surround gate improves the switching capacity of the TFTs.

Abstract translation: 3D存储器件的垂直切换层用于将一组垂直局部位线切换到相应的全局位线集合，垂直切换层是垂直薄膜晶体管（TFT）的TFT通道的2D阵列，其与 连接到本地位线阵列，每个TFT将局部位线切换到相应的全局位线。 阵列中的TFT分别具有沿着x轴和y轴的长度Lx和Ly的间隔，使得栅极材料层在xy平面内围绕每个TFT形成环绕栅，并且具有合并以形成行选择的厚度 沿x轴线，同时保持单独行选择线之间的长度Ls的间隔。 环绕栅极提高了TFT的开关容量。