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    Three-dimensional resistive random access memory containing self-aligned memory elements
    1.
    发明授权
    Three-dimensional resistive random access memory containing self-aligned memory elements 有权

    公开(公告)号：US10096654B2

    公开(公告)日：2018-10-09

    申请号：US14851296

    申请日：2015-09-11

    Applicant: SanDisk 3D LLC

    Inventor： Shin Kikuchi ,  Kazushi Komeda ,  Takuya Futase ,  Teruyuki Mine ,  Seje Takaki ,  Eiji Hayashi ,  Toshihide Tobitsuka

    IPC: H01L27/24 ,  H01L45/00

    Abstract: An alternating material stack of insulator lines and first electrically conductive material layers is formed over a substrate, and is patterned to provide alternating stacks of insulating layers and first electrically conductive lines. A metal can be selectively deposited on the physically exposed sidewalls of the first electrically conductive material layers to form metal lines, while not growing from the surfaces of the insulator lines. The metal lines are oxidized to form metal oxide lines that are self-aligned to the sidewalls of the first electrically conductive lines. Vertically extending second electrically conductive lines can be formed as a two-dimensional array of generally pillar-shaped structures between the alternating stacks of the insulator lines and the first electrically conductive lines. Each portion of the metal oxide lines at junctions of first and second electrically conductive lines constitute a resistive memory element for a resistive random access memory (ReRAM) device.

    CONCAVE WORD LINE AND CONVEX INTERLAYER DIELECTRIC FOR PROTECTING A READ/WRITE LAYER
    2.
    发明申请
    CONCAVE WORD LINE AND CONVEX INTERLAYER DIELECTRIC FOR PROTECTING A READ/WRITE LAYER 有权
    用于保护读/写层的意大利文字线和CONVEX INTERLAYER介质

    公开(公告)号：US20160126455A1

    公开(公告)日：2016-05-05

    申请号：US14529731

    申请日：2014-10-31

    Applicant: SANDISK 3D LLC

    Inventor： Eiji Hayashi ,  Naohito Yanagida ,  Michiaki Sano ,  Akira Nakada

    IPC: H01L45/00

    CPC classification number: H01L45/16 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1273 ,  H01L45/141 ,  H01L45/145 ,  H01L45/1616

    Abstract: An alternating stack of electrically conductive layers and electrically insulating layers is formed over global bit lines formed on a substrate. The alternating stack is patterned to form a line stack of electrically conductive lines and electrically insulating lines. Trench isolation structures are formed within each trench to define a plurality of memory openings laterally spaced from one another by the line stack in one direction and by trench isolation structures in another direction. The electrically conductive lines are laterally recessed relative to sidewall surfaces of the electrically insulating lines. A read/write memory material is deposited in recesses, and is anisotropically etched so that a top surface of a global bit line is physically exposed at a bottom of each memory opening. An electrically conductive bit line is formed within each memory opening to form a resistive random access memory device.

    Abstract translation: 导电层和电绝缘层的交替堆叠形成在形成在衬底上的全局位线之上。 将交替堆叠图案化以形成导电线和电绝缘线的线堆叠。 沟槽隔离结构形成在每个沟槽内以限定通过线堆叠在一个方向上横向间隔开的多个存储器开口以及另一个方向上的沟槽隔离结构。 导电线相对于电绝缘线的侧壁表面横向凹入。 读/写存储器材料沉积在凹槽中，并且被各向异性地蚀刻，使得全局位线的顶表面物理地暴露在每个存储器开口的底部。 在每个存储器开口内形成导电位线以形成电阻随机存取存储器件。

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