公开(公告)号：US09368601B2

公开(公告)日：2016-06-14

申请号：US14193451

申请日：2014-02-28

Applicant: SanDisk 3D LLC

Inventor： Michiaki Sano ,  Kensuke Yamaguchi ,  Akira Nakada ,  Naohito Yanagida

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/04 ,  H01L27/115

CPC classification number: H01L29/66666 ,  H01L21/28238 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/7827

Abstract: A fabrication process for a vertical channel transistor provides a desired control gate-to-drain overlap and sufficient isolation between the control gate and an underlying metal line. A body of the transistor is formed on a metal line, such as in a pillar shape. The metal line is oxidized to form metal oxide regions having an expanded volume. A gate insulator material and a control gate material are then deposited. The resulting structure is etched to form separate control gates for each transistor, and to expose the metal oxide. A further etch is performed to remove the metal oxide, forming voids under and around the control gates. An insulation fills the voids. An example implementation is a vertical bit line memory device in which the transistors connect a vertical bit line to a horizontal bit line.

Abstract translation: 垂直沟道晶体管的制造工艺提供所需的控制栅 - 漏重叠以及控制栅极与下面的金属线之间的充分隔离。 晶体管的主体形成在诸如柱状的金属线上。 金属线被氧化形成具有膨胀体积的金属氧化物区域。 然后沉积栅极绝缘体材料和控制栅极材料。 蚀刻所得到的结构以形成用于每个晶体管的单独的控制栅极，并暴露金属氧化物。 执行另外的蚀刻以去除金属氧化物，在控制栅极下和周围形成空隙。 绝缘填充空隙。 示例性实施例是垂直位线存储器件，其中晶体管将垂直位线连接到水平位线。

公开(公告)号：US09230905B2

公开(公告)日：2016-01-05

申请号：US14150162

申请日：2014-01-08

Applicant: SanDisk 3D LLC

Inventor： Seje Takaki ,  Michiaki Sano ,  Zhen Chen

IPC: H01L23/50 ,  H01L27/24 ,  H01L27/115 ,  H01L21/768 ,  H01L27/06

CPC classification number: H01L23/50 ,  H01L21/768 ,  H01L21/76838 ,  H01L21/76877 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/42332 ,  H01L29/7889 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multilevel device includes: at least one device region and at least one contact region having a stack of alternating plurality of continuous electrically conductive layers and plurality of electrically insulating layers located over a base. Each electrically conductive layer in the stack is electrically insulated from the other electrically conductive layers in the stack. The base may include a raised portion and a plurality of recesses in the raised portion, each recess in the plurality of recesses having a different lateral size from the other recesses in the plurality of recesses. The electrically conductive layers in the stack may be substantially conformal to the plurality of recesses in the base and expose one or more top surfaces of the raised portion of the base. A first electrically conductive layer in the stack may be a topmost layer in a laterally central portion of a first one of the plurality of recesses. A second electrically conductive layer in the stack different from the first electrically conductive layer may be a topmost layer in a laterally central portion of a second one of the plurality of recesses.

Abstract translation: 多电平装置包括：至少一个器件区域和至少一个接触区域，其具有交替的多个连续导电层和位于基极之上的多个电绝缘层的叠层。 堆叠中的每个导电层与堆叠中的其它导电层电绝缘。 基部可以包括凸起部分中的凸起部分和多个凹部，多个凹部中的每个凹部具有与多个凹部中的其它凹部不同的横向尺寸。 堆叠中的导电层可以基本上与基座中的多个凹部共形并且露出基部的凸起部分的一个或多个顶表面。 堆叠中的第一导电层可以是多个凹部中的第一个的横向中心部分中的最上层。 不同于第一导电层的堆叠中的第二导电层可以是多个凹部中的第二导电层的横向中心部分中的最上层。

公开(公告)号：US20150249143A1

公开(公告)日：2015-09-03

申请号：US14193451

申请日：2014-02-28

Applicant: SanDisk 3D LLC

Inventor： Michiaki Sano ,  Kensuke Yamaguchi ,  Akira Nakada ,  Naohito Yanagida

IPC: H01L29/66 ,  H01L29/04 ,  H01L21/28 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L29/66666 ,  H01L21/28238 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/7827

Abstract: A fabrication process for a vertical channel transistor provides a desired control gate-to-drain overlap and sufficient isolation between the control gate and an underlying metal line. A body of the transistor is formed on a metal line, such as in a pillar shape. The metal line is oxidized to form metal oxide regions having an expanded volume. A gate insulator material and a control gate material are then deposited. The resulting structure is etched to form separate control gates for each transistor, and to expose the metal oxide. A further etch is performed to remove the metal oxide, forming voids under and around the control gates. An insulation fills the voids. An example implementation is a vertical bit line memory device in which the transistors connect a vertical bit line to a horizontal bit line.

Abstract translation: 垂直沟道晶体管的制造工艺提供所需的控制栅 - 漏重叠以及控制栅极与下面的金属线之间的充分隔离。 晶体管的主体形成在诸如柱状的金属线上。 金属线被氧化形成具有膨胀体积的金属氧化物区域。 然后沉积栅极绝缘体材料和控制栅极材料。 蚀刻所得到的结构以形成用于每个晶体管的单独的控制栅极，并暴露金属氧化物。 执行另外的蚀刻以去除金属氧化物，在控制栅极下和周围形成空隙。 绝缘填充空隙。 示例性实施例是垂直位线存储器件，其中晶体管将垂直位线连接到水平位线。

公开(公告)号：US09666799B2

公开(公告)日：2017-05-30

申请号：US14529624

申请日：2014-10-31

Applicant: SANDISK 3D LLC

Inventor： Naohito Yanagida ,  Cheng Feng ,  Michiaki Sano ,  Akira Nakada ,  Steven J. Radigan ,  Eiji Hayashi

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/141 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1273 ,  H01L45/145 ,  H01L45/1616

Abstract: An alternating stack of electrically conductive layers and electrically insulating layers is formed over global bit lines formed on a substrate. The alternating stack is patterned to form a line stack of electrically conductive lines and electrically insulating lines. Trench isolation structures are formed within each trench to define a plurality of memory openings laterally spaced from one another by the line stack in one direction and by trench isolation structures in another direction. The electrically conductive lines are laterally recessed relative to sidewall surfaces of the electrically insulating lines. A read/write memory material is deposited in recesses, and is anisotropically etched so that a top surface of a global bit line is physically exposed at a bottom of each memory opening. An electrically conductive bit line is formed within each memory opening to form a resistive random access memory device.

公开(公告)号：US20150194380A1

公开(公告)日：2015-07-09

申请号：US14150162

申请日：2014-01-08

Applicant: SanDisk 3D LLC

Inventor： Seje Takaki ,  Michiaki Sano ,  Zhen Chen

IPC: H01L23/50 ,  H01L27/115 ,  H01L21/768 ,  H01L27/24

CPC classification number: H01L23/50 ,  H01L21/768 ,  H01L21/76838 ,  H01L21/76877 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/42332 ,  H01L29/7889 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multilevel device includes: at least one device region and at least one contact region having a stack of alternating plurality of continuous electrically conductive layers and plurality of electrically insulating layers located over a base. Each electrically conductive layer in the stack is electrically insulated from the other electrically conductive layers in the stack. The base may include a raised portion and a plurality of recesses in the raised portion, each recess in the plurality of recesses having a different lateral size from the other recesses in the plurality of recesses. The electrically conductive layers in the stack may be substantially conformal to the plurality of recesses in the base and expose one or more top surfaces of the raised portion of the base. A first electrically conductive layer in the stack may be a topmost layer in a laterally central portion of a first one of the plurality of recesses. A second electrically conductive layer in the stack different from the first electrically conductive layer may be a topmost layer in a laterally central portion of a second one of the plurality of recesses.

Abstract translation: 多电平装置包括：至少一个器件区域和至少一个接触区域，其具有交替的多个连续导电层和位于基极之上的多个电绝缘层的叠层。 堆叠中的每个导电层与堆叠中的其它导电层电绝缘。 基部可以包括凸起部分中的凸起部分和多个凹部，多个凹部中的每个凹部具有与多个凹部中的其它凹部不同的横向尺寸。 堆叠中的导电层可以基本上与基座中的多个凹部共形并且露出基部的凸起部分的一个或多个顶表面。 堆叠中的第一导电层可以是多个凹部中的第一个的横向中心部分中的最上层。 不同于第一导电层的堆叠中的第二导电层可以是多个凹部中的第二导电层的横向中心部分中的最上层。

公开(公告)号：US20160126455A1

公开(公告)日：2016-05-05

申请号：US14529731

申请日：2014-10-31

Applicant: SANDISK 3D LLC

Inventor： Eiji Hayashi ,  Naohito Yanagida ,  Michiaki Sano ,  Akira Nakada

IPC: H01L45/00

CPC classification number: H01L45/16 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1273 ,  H01L45/141 ,  H01L45/145 ,  H01L45/1616

Abstract: An alternating stack of electrically conductive layers and electrically insulating layers is formed over global bit lines formed on a substrate. The alternating stack is patterned to form a line stack of electrically conductive lines and electrically insulating lines. Trench isolation structures are formed within each trench to define a plurality of memory openings laterally spaced from one another by the line stack in one direction and by trench isolation structures in another direction. The electrically conductive lines are laterally recessed relative to sidewall surfaces of the electrically insulating lines. A read/write memory material is deposited in recesses, and is anisotropically etched so that a top surface of a global bit line is physically exposed at a bottom of each memory opening. An electrically conductive bit line is formed within each memory opening to form a resistive random access memory device.

Abstract translation: 导电层和电绝缘层的交替堆叠形成在形成在衬底上的全局位线之上。 将交替堆叠图案化以形成导电线和电绝缘线的线堆叠。 沟槽隔离结构形成在每个沟槽内以限定通过线堆叠在一个方向上横向间隔开的多个存储器开口以及另一个方向上的沟槽隔离结构。 导电线相对于电绝缘线的侧壁表面横向凹入。 读/写存储器材料沉积在凹槽中，并且被各向异性地蚀刻，使得全局位线的顶表面物理地暴露在每个存储器开口的底部。 在每个存储器开口内形成导电位线以形成电阻随机存取存储器件。

公开(公告)号：US09620712B2

公开(公告)日：2017-04-11

申请号：US14529731

申请日：2014-10-31

Applicant: SANDISK 3D LLC

Inventor： Eiji Hayashi ,  Naohito Yanagida ,  Michiaki Sano ,  Akira Nakada

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/16 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1273 ,  H01L45/141 ,  H01L45/145 ,  H01L45/1616

Abstract: An alternating stack of electrically conductive layers and electrically insulating layers is formed over global bit lines formed on a substrate. The alternating stack is patterned to form a line stack of electrically conductive lines and electrically insulating lines. Trench isolation structures are formed within each trench to define a plurality of memory openings laterally spaced from one another by the line stack in one direction and by trench isolation structures in another direction. The electrically conductive lines are laterally recessed relative to sidewall surfaces of the electrically insulating lines. A read/write memory material is deposited in recesses, and is anisotropically etched so that a top surface of a global bit line is physically exposed at a bottom of each memory opening. An electrically conductive bit line is formed within each memory opening to form a resistive random access memory device.

公开(公告)号：US20160126292A1

公开(公告)日：2016-05-05

申请号：US14529624

申请日：2014-10-31

Applicant: SANDISK 3D LLC

Inventor： Naohito Yanagida ,  Cheng Feng ,  Michiaki Sano ,  Akira Nakada ,  Steven J. Radigan ,  Eiji Hayashi

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L45/141 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1273 ,  H01L45/145 ,  H01L45/1616

Abstract: An alternating stack of electrically conductive layers and electrically insulating layers is formed over global bit lines formed on a substrate. The alternating stack is patterned to form a line stack of electrically conductive lines and electrically insulating lines. Trench isolation structures are formed within each trench to define a plurality of memory openings laterally spaced from one another by the line stack in one direction and by trench isolation structures in another direction. The electrically conductive lines are laterally recessed relative to sidewall surfaces of the electrically insulating lines. A read/write memory material is deposited in recesses, and is anisotropically etched so that a top surface of a global bit line is physically exposed at a bottom of each memory opening. An electrically conductive bit line is formed within each memory opening to form a resistive random access memory device.

公开(公告)号：US09177964B2

公开(公告)日：2015-11-03

申请号：US14099084

申请日：2013-12-06

Applicant: SanDisk 3D LLC

Inventor： Akira Nakada ,  Michiaki Sano ,  Naohito Yanagida ,  Teruyuki Mine

IPC: H01L27/115 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L27/24

CPC classification number: H01L27/115 ,  H01L21/2815 ,  H01L27/2454 ,  H01L27/249 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of forming sidewall gates for vertical transistors includes depositing a gate dielectric layer over polysilicon channel structures, and depositing a gate polysilicon layer over the gate dielectric. The gate polysilicon layer is then etched back to form separated gate electrodes. Filler portions are then formed between gate electrodes, which are then etched from the top down while their sides are protected.

Abstract translation: 形成用于垂直晶体管的侧壁栅极的方法包括在多晶硅沟道结构上沉积栅极介电层，以及在栅极电介质上沉积栅极多晶硅层。 然后将栅极多晶硅层回蚀刻形成分离的栅电极。 然后在栅电极之间形成填料部分，然后在其边被保护的同时从顶部向下蚀刻。

公开(公告)号：US20150162338A1

公开(公告)日：2015-06-11

申请号：US14099084

申请日：2013-12-06

Applicant: SanDisk 3D LLC

Inventor： Akira Nakada ,  Michiaki Sano ,  Naohito Yanagida ,  Teruyuki Mine

IPC: H01L27/115 ,  H01L29/78

CPC classification number: H01L27/115 ,  H01L21/2815 ,  H01L27/2454 ,  H01L27/249 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of forming sidewall gates for vertical transistors includes depositing a gate dielectric layer over polysilicon channel structures, and depositing a gate polysilicon layer over the gate dielectric. The gate polysilicon layer is then etched back to form separated gate electrodes. Filler portions are then formed between gate electrodes, which are then etched from the top down while their sides are protected.

Abstract translation: 形成用于垂直晶体管的侧壁栅极的方法包括在多晶硅沟道结构上沉积栅极介电层，以及在栅极电介质上沉积栅极多晶硅层。 然后将栅极多晶硅层回蚀刻形成分离的栅电极。 然后在栅电极之间形成填料部分，然后在其边被保护的同时从顶部向下蚀刻。