公开(公告)号：US20150249143A1

公开(公告)日：2015-09-03

申请号：US14193451

申请日：2014-02-28

Applicant: SanDisk 3D LLC

Inventor： Michiaki Sano ,  Kensuke Yamaguchi ,  Akira Nakada ,  Naohito Yanagida

IPC: H01L29/66 ,  H01L29/04 ,  H01L21/28 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L29/66666 ,  H01L21/28238 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/7827

Abstract: A fabrication process for a vertical channel transistor provides a desired control gate-to-drain overlap and sufficient isolation between the control gate and an underlying metal line. A body of the transistor is formed on a metal line, such as in a pillar shape. The metal line is oxidized to form metal oxide regions having an expanded volume. A gate insulator material and a control gate material are then deposited. The resulting structure is etched to form separate control gates for each transistor, and to expose the metal oxide. A further etch is performed to remove the metal oxide, forming voids under and around the control gates. An insulation fills the voids. An example implementation is a vertical bit line memory device in which the transistors connect a vertical bit line to a horizontal bit line.

Abstract translation: 垂直沟道晶体管的制造工艺提供所需的控制栅 - 漏重叠以及控制栅极与下面的金属线之间的充分隔离。 晶体管的主体形成在诸如柱状的金属线上。 金属线被氧化形成具有膨胀体积的金属氧化物区域。 然后沉积栅极绝缘体材料和控制栅极材料。 蚀刻所得到的结构以形成用于每个晶体管的单独的控制栅极，并暴露金属氧化物。 执行另外的蚀刻以去除金属氧化物，在控制栅极下和周围形成空隙。 绝缘填充空隙。 示例性实施例是垂直位线存储器件，其中晶体管将垂直位线连接到水平位线。

公开(公告)号：US09368601B2

公开(公告)日：2016-06-14

申请号：US14193451

申请日：2014-02-28

Applicant: SanDisk 3D LLC

Inventor： Michiaki Sano ,  Kensuke Yamaguchi ,  Akira Nakada ,  Naohito Yanagida

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/04 ,  H01L27/115

CPC classification number: H01L29/66666 ,  H01L21/28238 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/7827

Abstract: A fabrication process for a vertical channel transistor provides a desired control gate-to-drain overlap and sufficient isolation between the control gate and an underlying metal line. A body of the transistor is formed on a metal line, such as in a pillar shape. The metal line is oxidized to form metal oxide regions having an expanded volume. A gate insulator material and a control gate material are then deposited. The resulting structure is etched to form separate control gates for each transistor, and to expose the metal oxide. A further etch is performed to remove the metal oxide, forming voids under and around the control gates. An insulation fills the voids. An example implementation is a vertical bit line memory device in which the transistors connect a vertical bit line to a horizontal bit line.

Abstract translation: 垂直沟道晶体管的制造工艺提供所需的控制栅 - 漏重叠以及控制栅极与下面的金属线之间的充分隔离。 晶体管的主体形成在诸如柱状的金属线上。 金属线被氧化形成具有膨胀体积的金属氧化物区域。 然后沉积栅极绝缘体材料和控制栅极材料。 蚀刻所得到的结构以形成用于每个晶体管的单独的控制栅极，并暴露金属氧化物。 执行另外的蚀刻以去除金属氧化物，在控制栅极下和周围形成空隙。 绝缘填充空隙。 示例性实施例是垂直位线存储器件，其中晶体管将垂直位线连接到水平位线。