Abstract:
A memory is described that includes a shared diode layer and a memory element coupled to the diode layer. The memory element has a pie slice-shape, and includes a sidewall having a carbon film thereon. Numerous other aspects are also disclosed.
Abstract:
A method is provided that includes forming completely distinct first features above a substrate, forming sidewall spacers on the first features, filling spaces between adjacent sidewall spacers with filler features, and removing the sidewall spacers. Numerous other aspects are provided.
Abstract:
A method is provided that includes forming completely distinct first features above a substrate, forming sidewall spacers on the first features, filling spaces between adjacent sidewall spacers with filler features, and removing the sidewall spacers. Numerous other aspects are provided.
Abstract:
In some aspects, a memory cell is provided that includes a first conducting layer, a reversible resistance switching element above the first conducting layer, a second conducting layer above the reversible resistance switching element, and a liner disposed about a sidewall of the reversible resistance switching element. The reversible resistance switching element includes a first metal oxide material, and the liner includes the first metal oxide material. Numerous other aspects are provided.
Abstract:
A memory is described that includes a shared diode layer and a memory element coupled to the diode layer. The memory element has a pie slice-shape, and includes a sidewall having a carbon film thereon. Numerous other aspects are also disclosed.