公开(公告)号：US09875987B2

公开(公告)日：2018-01-23

申请号：US15247393

申请日：2016-08-25

Applicant: Freescale Semiconductor, Inc.

Inventor： Lakshminarayan Viswanathan ,  Jaynal A. Molla

IPC: H01L23/00 ,  H01L29/16 ,  H01L21/48 ,  H01L29/20 ,  H01L23/66 ,  H01L23/48 ,  H01L21/78 ,  H01L23/31 ,  H01L23/36 ,  H01L23/367 ,  H01L23/482 ,  H01L21/683 ,  H01L23/495 ,  H01L21/56

CPC classification number: H01L24/83 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/4827 ,  H01L23/49513 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/741 ,  H01L24/743 ,  H01L24/92 ,  H01L24/94 ,  H01L29/16 ,  H01L29/2003 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/03312 ,  H01L2224/0332 ,  H01L2224/03436 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03505 ,  H01L2224/04026 ,  H01L2224/05009 ,  H01L2224/05018 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05551 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05794 ,  H01L2224/05839 ,  H01L2224/05844 ,  H01L2224/05847 ,  H01L2224/05855 ,  H01L2224/05864 ,  H01L2224/05887 ,  H01L2224/0589 ,  H01L2224/05893 ,  H01L2224/27002 ,  H01L2224/2731 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/27438 ,  H01L2224/27505 ,  H01L2224/29006 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29015 ,  H01L2224/29017 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/29084 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29116 ,  H01L2224/29117 ,  H01L2224/29118 ,  H01L2224/2912 ,  H01L2224/29124 ,  H01L2224/29138 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/2918 ,  H01L2224/29184 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29387 ,  H01L2224/2939 ,  H01L2224/29393 ,  H01L2224/29499 ,  H01L2224/296 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/741 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8346 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/1016 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1421 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/3512 ,  H01L2224/27 ,  H01L2224/11 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/01015 ,  H01L2924/01048 ,  H01L2924/01014 ,  H01L2924/01032 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01028 ,  H01L2924/01027 ,  H01L2924/01026 ,  H01L2224/03 ,  H01L2224/05099 ,  H01L2924/01006 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/01005 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2221/68304 ,  H01L21/304 ,  H01L2224/83 ,  H01L2924/0781 ,  H01L2924/00 ,  H01L2224/034 ,  H01L2221/68368 ,  H01L2224/274

Abstract: An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a conductive layer underlying the sintered metallic layer, and a conductive substrate underlying the conductive layer.

公开(公告)号：US09640514B1

公开(公告)日：2017-05-02

申请号：US15084004

申请日：2016-03-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wei Lin ,  Troy L. Graves-Abe ,  Donald F. Canaperi ,  Spyridon Skordas ,  Matthew T. Shoudy ,  Binglin Miao ,  Raghuveer R. Patlolla ,  Sanjay C. Mehta

IPC: H01L25/065 ,  H01L21/762 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/76251 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/29084 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/83031 ,  H01L2224/83193 ,  H01L2224/832 ,  H01L2224/83896 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01008 ,  H01L2924/01014 ,  H01L2924/0503 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/20109 ,  H01L2924/206 ,  H01L2924/2064

Abstract: A bonding material stack for wafer-to-wafer bonding is provided. The bonding material stack may include a plurality of layers each including boron and nitrogen. In one embodiment, the plurality of layers may include: a first boron oxynitride layer for adhering to a wafer; a boron nitride layer over the first boron oxynitride layer; a second boron oxynitride layer over the boron nitride layer; and a silicon-containing boron oxynitride layer over the second boron oxynitride layer.

公开(公告)号：US20160027759A1

公开(公告)日：2016-01-28

申请号：US14773970

申请日：2014-03-24

Applicant: OSRAM OPTO SEMICONDUCTORS GMBH

Inventor： Andreas Plößl

IPC: H01L23/00 ,  H01L21/288 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L24/83 ,  H01L21/2855 ,  H01L21/2885 ,  H01L21/76874 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/27444 ,  H01L2224/2745 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/29084 ,  H01L2224/29109 ,  H01L2224/29113 ,  H01L2224/29139 ,  H01L2224/29166 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32505 ,  H01L2224/83054 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83359 ,  H01L2224/83539 ,  H01L2224/83825 ,  H01L2224/83902 ,  H01L2224/83948 ,  H01L2924/12041 ,  H01L2924/01083 ,  H01L2924/00012 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method is provided for connecting parts to be joined. A first layer sequence is applied to a first part to be joined. The first layer sequence contains silver. A second layer sequence is applied to a second part to be joined. The second layer sequence contains indium and bismuth. The first layer sequence and the second layer sequence are pressed together at their end faces respectively remote from the first part to be joined and the second part to be joined through application of a joining pressure at a joining temperature which amounts to at most 120° C. for a predetermined joining time. The first layer sequence and the second layer sequence fuse together to form a bonding layer which directly adjoins the first part to be joined and the second part to be joined and the melting temperature of which amounts to at least 260° C.

Abstract translation: 提供了用于连接要连接的部件的方法。 将第一层序列应用于要接合的第一部分。 第一层序列包含银。 将第二层序列应用于待连接的第二部分。 第二层序列包含铟和铋。 第一层序列和第二层序列在其端面处被压在一起，分别远离待接合的第一部分和待连接的第二部分，通过在接合温度下施加接合压力达到至多120℃ 预定的接合时间。 第一层序列和第二层序列熔合在一起形成直接毗邻待接合的第一部分和待接合的第二部分的接合层，其熔融温度等于至少260℃。

公开(公告)号：US20150069597A1

公开(公告)日：2015-03-12

申请号：US14322216

申请日：2014-07-02

Applicant: Kabushiki Kaisha Toshiba

Inventor： Keiichi MATSUSHITA ,  Yo SASAKI

IPC: H01L23/373 ,  H01L23/00

CPC classification number: H01L23/3736 ,  H01L21/50 ,  H01L23/10 ,  H01L23/142 ,  H01L23/4827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L2224/0346 ,  H01L2224/04026 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05647 ,  H01L2224/2741 ,  H01L2224/2743 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/29084 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/32245 ,  H01L2224/32501 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83359 ,  H01L2224/83379 ,  H01L2224/83447 ,  H01L2224/83825 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/161 ,  H01L2924/16195 ,  H01L2924/163 ,  H01L2924/171 ,  H01L2924/2064 ,  H01L2224/05644 ,  H01L2924/00012 ,  H01L2224/06164 ,  H01L2224/45099

Abstract: According to one embodiment, a semiconductor device includes a semiconductor element, a mounting member including Cu, and a bonding layer provided between the semiconductor element and the mounting member. The bonding layer includes a first region including Ti and Cu, and a second region provided between the first region and the mounting member, and including Sn and Cu. A first position along the first direction is positioned between the semiconductor element and a second position along the first direction. The first position is where the composition ratio of Ti in the first region is 0.1 times a maximum value of the composition ratio of Ti. The second position is where the composition ratio of Sn in the second region is 0.1 times a maximum value of the composition ratio of Sn. A distance between the first position and the second position is not less than 0.1 micrometers.

Abstract translation: 根据一个实施例，半导体器件包括半导体元件，包括Cu的安装构件和设置在半导体元件和安装构件之间的接合层。 接合层包括包括Ti和Cu的第一区域，以及设置在第一区域和安装构件之间的包括Sn和Cu的第二区域。 沿着第一方向的第一位置位于半导体元件和沿第一方向的第二位置之间。 第一位置是第一区域中的Ti的组成比为Ti的组成比的最大值的0.1倍。 第二位置是第二区域中的Sn的组成比为Sn的组成比的最大值的0.1倍。 第一位置和第二位置之间的距离不小于0.1微米。

公开(公告)号：US08742600B2

公开(公告)日：2014-06-03

申请号：US13736088

申请日：2013-01-08

Applicant: Industrial Technology Research Institute

Inventor： Jing-Yao Chang ,  Tao-Chih Chang ,  Tung-Han Chuang ,  Chun-Yen Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/49811 ,  H01L21/76885 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/29005 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/29084 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/83065 ,  H01L2224/8309 ,  H01L2224/83091 ,  H01L2224/83097 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/8381 ,  H01L2224/83825 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2924/206 ,  H01L2924/00014

Abstract: Provided are a dual-phase intermetallic interconnection structure and a fabricating method thereof. The dual-phase intermetallic interconnection structure includes a first intermetallic compound, a second intermetallic compound, a first solder layer, and a second solder layer. The second intermetallic compound covers and surrounds the first intermetallic compound. The first intermetallic compound and the second intermetallic compound contain different high-melting point metal. The first solder layer and the second solder layer are disposed at the opposite sides of the second intermetallic compound, respectively. The first intermetallic compound is adapted to fill the micropore defects generated during the formation of the second intermetallic compound.

Abstract translation: 提供了一种双相金属间互连结构及其制造方法。 双相金属间互连结构包括第一金属间化合物，第二金属间化合物，第一焊料层和第二焊料层。 第二金属间化合物覆盖并围绕第一金属间化合物。 第一金属间化合物和第二金属间化合物含有不同的高熔点金属。 第一焊料层和第二焊料层分别设置在第二金属间化合物的相对侧。 第一金属间化合物适于填充在形成第二金属间化合物期间产生的微孔缺陷。

公开(公告)号：US20100055842A1

公开(公告)日：2010-03-04

申请号：US12549739

申请日：2009-08-28

Applicant: Yuki Sugo ,  Sedahito Misumi ,  Takeshi Matsumura

Inventor： Yuki Sugo ,  Sedahito Misumi ,  Takeshi Matsumura

IPC: H01L21/60 ,  C08L63/00 ,  B32B27/38

CPC classification number: H01L21/6836 ,  C08G59/621 ,  C08L33/06 ,  C08L2666/04 ,  C09J163/00 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2224/274 ,  H01L2224/29 ,  H01L2224/29084 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/85001 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/3025 ,  Y10T428/31511 ,  H01L2924/0635 ,  H01L2924/066 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/05442 ,  H01L2924/0532 ,  H01L2924/05432 ,  H01L2924/05032 ,  H01L2924/0503 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

Abstract: The thermosetting die-bonding film of the present invention is used in manufacturing a semiconductor device, has at least an epoxy resin, a phenol resin, and an acrylic copolymer, and the ratio X/Y is 0.7 to 5 when X represents a total weight of the epoxy resin and the phenol resin and Y represents a weight of the acrylic copolymer.

Abstract translation: 本发明的热固性芯片接合薄膜用于制造半导体器件，至少具有环氧树脂，酚醛树脂和丙烯酸共聚物，当X表示总重量时，X / Y的比率为0.7〜5 的环氧树脂和酚醛树脂，Y表示丙烯酸共聚物的重量。

公开(公告)号：US06861285B2

公开(公告)日：2005-03-01

申请号：US10407534

申请日：2003-04-04

Applicant: Rajen C. Dias

Inventor： Rajen C. Dias

IPC: H01L21/44 ,  H01L21/56 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/563 ,  H01L24/11 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/1184 ,  H01L2224/13111 ,  H01L2224/2784 ,  H01L2224/27901 ,  H01L2224/29 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/29084 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/29393 ,  H01L2224/73104 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/05442 ,  H01L2924/05432 ,  H01L2924/05032 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

Abstract: A die with flip chip bumps including at least one layer of filled underfill on the die surface and a layer of unfilled underfill over the filled underfill and the flip chip bumps. An IC assembly including a substrate with bumps and at least one layer of filled underfill on the substrate surface and a layer of unfilled underfill over the filled underfill and the bumps. A die or IC assembly with a plurality of filled underfill layers with differing CTE. Methods of making the dies and IC assemblies.

Abstract translation: 具有倒装芯片凸块的模具，其包括在模具表面上的至少一层填充的底部填充物和在填充的底部填充物和倒装芯片凸块上的未填充的底部填充层。 一种IC组件，其包括具有凸起的衬底和在衬底表面上的至少一层填充的底部填充物和在填充的底部填充物和凸块上的未填充的底部填充物层。 具有不同CTE的多个填充的底部填充层的模具或IC组件。 制造模具和IC组件的方法。

公开(公告)号：US20030203536A1

公开(公告)日：2003-10-30

申请号：US10407534

申请日：2003-04-04

Inventor： Rajen C. Dias

IPC: H01L021/44

CPC classification number: H01L21/563 ,  H01L24/11 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/1184 ,  H01L2224/13111 ,  H01L2224/2784 ,  H01L2224/27901 ,  H01L2224/29 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/29084 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/29393 ,  H01L2224/73104 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/05442 ,  H01L2924/05432 ,  H01L2924/05032 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

Abstract: A die with flip chip bumps including at least one layer of filled underfill on the die surface and a layer of unfilled underfill over the filled underfill and the flip chip bumps. An IC assembly including a substrate with bumps and at least one layer of filled underfill on the substrate surface and a layer of unfilled underfill over the filled underfill and the bumps. A die or IC assembly with a plurality of filled underfill layers with differing CTE. Methods of making the dies and IC assemblies.

公开(公告)号：US4757934A

公开(公告)日：1988-07-19

申请号：US011670

申请日：1987-02-06

Applicant: Bernard Greenstein

Inventor： Bernard Greenstein

IPC: B23K1/19 ,  B23K35/00 ,  H01L21/58 ,  H01L21/60 ,  H01L23/373 ,  B23K31/02 ,  B23K35/36

CPC classification number: H01L24/83 ,  B23K1/19 ,  B23K35/002 ,  H01L23/3735 ,  H01L24/27 ,  H01L24/32 ,  B23K2035/008 ,  H01L2224/04026 ,  H01L2224/2908 ,  H01L2224/29084 ,  H01L2224/29111 ,  H01L2224/2918 ,  H01L2224/29184 ,  H01L2224/29186 ,  H01L2224/32245 ,  H01L2224/8319 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/15724 ,  H01L2924/351

Abstract: A semiconductor die is mounted on a metal substrate via intermediate layers which permit the die to be readily soldered to the combination while yet reducing thermal stresses. A dielectric layer is formed over the substrate, followed by another layer of a selected metal, either molybdenum or tungsten. Atop the metal layer is another layer comprising a mixture of solder and the selected metal. A layer of only solder is formed over the mixture, and the semiconductor die is bonded thereto by means of the layer of solder.

Abstract translation: 通过中间层将半导体管芯安装在金属基板上，允许模具容易地焊接到组合，同时还减少热应力。 在衬底上形成介电层，随后是另一层选择的金属，即钼或钨。 金属层顶部是另一层，包括焊料和所选金属的混合物。 在混合物上形成仅一层焊料，半导体管芯通过焊料层与其结合。

公开(公告)号：US11683963B2

公开(公告)日：2023-06-20

申请号：US16249387

申请日：2019-01-16

Applicant: Samsung Display Co., Ltd.

Inventor： Chungseok Lee ,  Donghee Park ,  Cheolgeun An ,  Jihoon Oh ,  Euiyun Jang ,  Jeongho Hwang

IPC: H01L27/32 ,  H01L23/00 ,  H01L51/00

CPC classification number: H01L27/3276 ,  H01L24/29 ,  H01L24/32 ,  H01L51/0096 ,  H01L2224/13144 ,  H01L2224/16238 ,  H01L2224/271 ,  H01L2224/294 ,  H01L2224/29005 ,  H01L2224/29028 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/29083 ,  H01L2224/29084 ,  H01L2224/29293 ,  H01L2224/29391 ,  H01L2224/29439 ,  H01L2224/29444 ,  H01L2224/29447 ,  H01L2224/29455 ,  H01L2224/29499 ,  H01L2224/32148 ,  H01L2224/32225 ,  H01L2224/32238 ,  H01L2224/743 ,  H01L2224/81191 ,  H01L2224/81903 ,  H01L2224/831 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83345 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2251/5369 ,  H01L2924/07811 ,  H01L2924/1426 ,  H01L2224/29444 ,  H01L2924/00014 ,  H01L2224/29439 ,  H01L2924/00014 ,  H01L2224/29447 ,  H01L2924/00014 ,  H01L2224/29455 ,  H01L2924/00014 ,  H01L2224/2929 ,  H01L2924/0665 ,  H01L2224/29005 ,  H01L2924/00012 ,  H01L2224/9211 ,  H01L2224/81 ,  H01L2224/83

Abstract: An anisotropic conductive film includes a conductive layer; a first resin insulating layer over a first surface of the conductive layer; and a second resin insulating layer over a second surface of the conductive layer, wherein the conductive layer comprises a plurality of conductive particles and a nano fiber connecting the plurality of conductive particles to each other, each of the plurality of conductive particles comprising a plurality of needle-shaped protrusions having a conical shape, and wherein the first resin insulating layer and the second resin insulating layer comprise a same material and have different thicknesses.