公开(公告)号：US20230301051A1

公开(公告)日：2023-09-21

申请号：US18320494

申请日：2023-05-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jhon Jhy Liaw

IPC: H10B10/00 ,  G11C11/419 ,  H01L23/528 ,  H01L29/78 ,  H01L29/08 ,  H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238

CPC classification number: H10B10/125 ,  G11C11/419 ,  H01L23/5286 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/41733 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/41791 ,  H01L29/66545 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823871 ,  H10B10/12 ,  H10B10/18

Abstract: A semiconductor structure includes first and second SRAM cells disposed over a substrate. Each first SRAM cell includes at least two first p-type transistors and four first n-type transistors. Each first p-type and n-type transistors includes a channel in a single semiconductor fin. Each second SRAM cell includes at least two second p-type transistors and four second n-type transistors. Each second p-type transistors includes a channel in a single semiconductor fin. Each second n-type transistors includes a channel in multiple semiconductor fins. The source/drain regions of the first p-type transistors are doped at a first dopant concentration, the source/drain regions of the second p-type transistors are doped at a second dopant concentration, and the first dopant concentration is greater than the second dopant concentration.

公开(公告)号：US20230282523A1

公开(公告)日：2023-09-07

申请号：US17688873

申请日：2022-03-07

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  REINALDO VEGA ,  Praneet Adusumilli ,  Cheng Chi

IPC: H01L21/8238 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L29/517 ,  H01L29/518 ,  H01L29/4958 ,  H01L29/4966

Abstract: A transistor structure includes a semiconductor substrate; an NFET channel structure atop the substrate; a PFET channel structure atop the substrate; a first dielectric atop the PFET channel structure; a second dielectric atop the NFET channel structure; a shared internal metal gate atop the dielectrics; a shared ferroelectric layer atop the shared internal metal gate; and a shared external gate electrode atop the shared ferroelectric layer. The first and second dielectrics are doped with different metals that provide differing overall work functions for the PFET and the NFET. A method for making a transistor structure includes depositing a shared dielectric onto an NFET channel structure and a PFET channel structure, and converting the shared dielectric to a first high-k dielectric atop the PFET channel structure and a second high-k dielectric atop the NFET channel structure. The first high-k dielectric and the second high-k dielectric are doped with different metals.

公开(公告)号：US20230268340A1

公开(公告)日：2023-08-24

申请号：US18141300

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chih YU ,  Chien-Mao Chen

IPC: H01L27/06 ,  H01C17/14 ,  H01L21/8238 ,  H01L27/01 ,  H01C7/00

CPC classification number: H01L27/0629 ,  H01C17/14 ,  H01L21/823878 ,  H01L28/24 ,  H01L27/016 ,  H01C7/006 ,  H01L21/823842

Abstract: A semiconductor device includes: a metal thin film disposed on a semiconductor substrate; and first and second contact structures disposed on the metal thin film, wherein the first and second contact structures are laterally spaced from each other by a dummy layer that comprises at least one polishing resistance material.

公开(公告)号：US20230245931A1

公开(公告)日：2023-08-03

申请号：US18180139

申请日：2023-03-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： TUNG-HUANG CHEN ,  YEN-YU CHEN ,  PO-AN CHEN ,  SOON-KANG HUANG

IPC: H01L21/8238 ,  H01L27/092 ,  H01L23/535 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/321

CPC classification number: H01L21/82385 ,  H01L27/092 ,  H01L23/535 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/3212 ,  H01L21/823842 ,  H01L21/28088

Abstract: A method of manufacturing a semiconductor device having metal gates and the semiconductor device are disclosed. The method comprises providing a first sacrificial gate associated with a first conductive type transistor and a second sacrificial gate associated with a second conductive type transistor disposed over the substrate, wherein the first conductive type and the second conductive type are complementary; replacing the first sacrificial gate with a first metal gate structure; forming a patterned dielectric layer and/or a patterned photoresist layer to cover the first metal gate structure; and replacing the second sacrificial gate with a second metal gate structure. The method can improve gate height uniformity during twice metal gate chemical mechanical polish processes.

公开(公告)号：US20230207563A1

公开(公告)日：2023-06-29

申请号：US17565367

申请日：2021-12-29

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Julien Frougier ,  Ruilong Xie

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/02532 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742

Abstract: A complementary metal-oxide-semiconductor field effect transistor structure (C-MOSFET) includes a substrate; a dielectric pillar that is embedded in and recessed into the substrate; a gate pillar that contacts the dielectric pillar and protrudes from the substrate; a first stack of semiconductor nanosheets that protrude from a first side of the gate pillar; and a second stack of semiconductor nanosheets that protrude from a second side of the gate pillar, opposite the first side.

公开(公告)号：US11688786B2

公开(公告)日：2023-06-27

申请号：US17189779

申请日：2021-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/4908 ,  H01L21/02603 ,  H01L21/28088 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

Abstract: In an embodiment, a device includes: a first channel region; a second channel region; and a gate structure around the first channel region and the second channel region, the gate structure including: a gate dielectric layer; a first p-type work function metal on the gate dielectric layer, the first p-type work function metal including fluorine and aluminum; a second p-type work function metal on the first p-type work function metal, the second p-type work function metal having a lower concentration of fluorine and a lower concentration of aluminum than the first p-type work function metal; and a fill layer on the second p-type work function metal.

公开(公告)号：US11682716B2

公开(公告)日：2023-06-20

申请号：US16902190

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Jui-Ping Chuang ,  Chen-Hsiang Lu ,  Yu-Cheng Liu ,  Wei-Ting Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/49 ,  H01L29/51 ,  H01L21/311 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/1608 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/785 ,  H01L29/7848 ,  H01L29/7851

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.

公开(公告)号：US11682589B2

公开(公告)日：2023-06-20

申请号：US17068041

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Wen Chiu ,  Da-Yuan Lee ,  Hsien-Ming Lee ,  Kai-Cyuan Yang ,  Yu-Sheng Wang ,  Chih-Hsiang Fan ,  Kun-Wa Kuok

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L21/823821 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517

Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.

公开(公告)号：US11670632B2

公开(公告)日：2023-06-06

申请号：US16939463

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chih Yu ,  Chien-Mao Chen

IPC: H01L27/06 ,  H01C17/14 ,  H01L21/8238 ,  H01L27/01 ,  H01C7/00 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01C7/006 ,  H01C17/14 ,  H01L21/823878 ,  H01L27/016 ,  H01L28/24 ,  H01L21/823842

Abstract: A semiconductor device includes: a metal thin film disposed on a semiconductor substrate; and first and second contact structures disposed on the metal thin film, wherein the first and second contact structures are laterally spaced from each other by a dummy layer that comprises at least one polishing resistance material.

公开(公告)号：US11664366B2

公开(公告)日：2023-05-30

申请号：US17481300

申请日：2021-09-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L21/8238 ,  H01L27/02 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L27/0207 ,  H01L21/82385 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785 ,  H10B10/12

Abstract: A layout of a semiconductor device and a method of forming a semiconductor device, the semiconductor device include a first fin and a second fin disposed on a substrate, a gate and a spacer. The first fin and the second fin both include two opposite edges, and the gate completely covers the two opposite edges of the first fin and only covers one sidewall of the two opposite edges of the second fin. The spacer is disposed at two sides of the gate, and the spacer covers another sidewall of the two opposite edges of the second fin.