专利检索 cpc:"H01L2224/85416" 第 3 页

21.

发明申请
SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：半导体封装及其制造方法

公开(公告)号：US20150125996A1

公开(公告)日：2015-05-07

申请号：US14595638

申请日：2015-01-13

申请人： Doojin Kim , Youngsik Kim , Kitaik Oh , Sungbok Hong

发明人： Doojin Kim , Youngsik Kim , Kitaik Oh , Sungbok Hong

IPC分类号： H01L23/00

CPC分类号： H01L24/85 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/78 , H01L25/0657 , H01L2224/04042 , H01L2224/05624 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/4809 , H01L2224/48145 , H01L2224/48147 , H01L2224/48227 , H01L2224/48465 , H01L2224/48599 , H01L2224/48616 , H01L2224/48624 , H01L2224/48992 , H01L2224/48997 , H01L2224/73265 , H01L2224/78301 , H01L2224/85181 , H01L2224/85365 , H01L2224/85416 , H01L2224/85951 , H01L2224/85986 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2224/48455

摘要： A semiconductor package comprises a board including a board pad, a plurality of semiconductor chips mounted on the board, the semiconductor chips including chip pads. Bumps are disposed on the chip pads, respectively, and a wire is disposed between the chip pads and the bumps. The wire electrically connects the chip pads of the plurality of semiconductor chips and the board pad to each other.

摘要翻译： 半导体封装包括板，其包括板焊盘，安装在板上的多个半导体芯片，包括芯片焊盘的半导体芯片。凸块分别设置在芯片焊盘上，并且引线布置在芯片焊盘和凸块之间。导线将多个半导体芯片的芯片焊盘与板焊盘彼此电连接。

22.

发明申请
SYSTEMS AND METHODS TO FABRICATE A RADIO FREQUENCY INTEGRATED CIRCUIT 审中-公开
标题翻译：无线电频率综合电路的系统和方法

公开(公告)号：US20150044863A1

公开(公告)日：2015-02-12

申请号：US14525632

申请日：2014-10-28

申请人： Skyworks Solutions, Inc.

发明人： Weimin Sun , Peter J. Zampardi, JR. , Hongxiao Shao

IPC分类号： H01L23/00

CPC分类号： H01L23/66 , C25D5/022 , C25D5/12 , C25D7/0607 , C25D17/00 , H01L23/49838 , H01L23/49866 , H01L24/03 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L2223/6605 , H01L2223/6611 , H01L2224/03424 , H01L2224/03462 , H01L2224/03464 , H01L2224/04042 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05644 , H01L2224/45144 , H01L2224/45147 , H01L2224/48095 , H01L2224/48229 , H01L2224/48644 , H01L2224/48655 , H01L2224/48664 , H01L2224/49111 , H01L2224/85205 , H01L2224/85411 , H01L2224/85416 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/85464 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/1421 , H01L2924/15747 , H01L2924/2064 , H05K1/0243 , H05K1/09 , H05K1/111 , H05K3/10 , H05K3/244 , H05K3/3452 , H05K2203/049 , H05K2203/0597 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099

摘要： To reduce radio frequency (RF) losses during operation of a radio frequency integrated circuit (RFIC) module, the RFIC module is fabricated such that at least one of an edge of the wirebond pad on the copper trace and a sidewall of the copper trace is free from high-resistivity plating material. The unplated portion provides a path for the RF current to flow around the high-resistivity material, which reduces the RF signal loss associated with the high resistivity plating material.

摘要翻译： 为了在射频集成电路（RFIC）模块的操作期间减少射频（RF）损耗，RFIC模块被制造成使得铜迹线上的引线键合的边缘和铜迹线的侧壁上的至少一个是没有高电阻率电镀材料。未镀层部分提供用于RF电流围绕高电阻率材料流动的路径，这降低了与高电阻率电镀材料相关联的RF信号损耗。

23.

发明申请
POWER AMPLIFIER MODULES INCLUDING RELATED SYSTEMS, DEVICES, AND METHODS 有权
标题翻译：功率放大器模块，包括相关系统，器件和方法

公开(公告)号：US20140002188A1

公开(公告)日：2014-01-02

申请号：US13917384

申请日：2013-06-13

申请人： SKYWORKS SOLUTIONS, INC.

发明人： Howard E. Chen , Yifan Guo , Dinhphuoc Vu Hoang , Mehran Janani , Tin Myint Ko , Philip John Lehtola , Anthony James LoBianco , Hardik Bhupendra Modi , Hoang Mong Nguyen , Matthew Thomas Ozalas , Sandra Louise Petty-Weeks , Matthew Sean Read , Jens Albrecht Riege , David Steven Ripley , Hongxiao Shao , Hong Shen , Weimin Sun , Hsiang-Chih Sun , Patrick Lawrence Welch , Peter J. Zampardi, JR. , Guohao Zhang

IPC分类号： H03F3/19

CPC分类号： H03F1/0205 , H01L21/485 , H01L21/4853 , H01L21/4864 , H01L21/565 , H01L21/76898 , H01L21/78 , H01L21/8249 , H01L21/8252 , H01L22/14 , H01L23/3114 , H01L23/481 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L23/49844 , H01L23/49861 , H01L23/49866 , H01L23/49894 , H01L23/50 , H01L23/522 , H01L23/552 , H01L23/66 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L24/97 , H01L27/0605 , H01L27/0623 , H01L27/092 , H01L29/0684 , H01L29/0821 , H01L29/0826 , H01L29/1004 , H01L29/20 , H01L29/205 , H01L29/36 , H01L29/66242 , H01L29/66863 , H01L29/737 , H01L29/7371 , H01L29/812 , H01L29/8605 , H01L2223/6611 , H01L2223/6616 , H01L2223/6644 , H01L2223/665 , H01L2223/6655 , H01L2224/05155 , H01L2224/05164 , H01L2224/05554 , H01L2224/05644 , H01L2224/45015 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48177 , H01L2224/48227 , H01L2224/48465 , H01L2224/48611 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2224/48664 , H01L2224/48811 , H01L2224/48816 , H01L2224/48844 , H01L2224/48847 , H01L2224/48855 , H01L2224/48864 , H01L2224/4903 , H01L2224/49111 , H01L2224/49176 , H01L2224/85205 , H01L2224/85207 , H01L2224/85411 , H01L2224/85416 , H01L2224/85444 , H01L2224/85455 , H01L2224/85464 , H01L2924/00011 , H01L2924/10253 , H01L2924/10329 , H01L2924/12033 , H01L2924/12042 , H01L2924/1305 , H01L2924/13051 , H01L2924/1306 , H01L2924/13091 , H01L2924/1421 , H01L2924/15747 , H01L2924/181 , H01L2924/19105 , H01L2924/19107 , H01L2924/3011 , H01L2924/30111 , H01L2924/3025 , H03F1/565 , H03F3/187 , H03F3/19 , H03F3/195 , H03F3/21 , H03F3/213 , H03F3/245 , H03F3/347 , H03F3/45 , H03F3/60 , H03F2200/387 , H03F2200/451 , H03F2200/48 , H03F2200/555 , H01L2924/00 , H01L2924/00014

摘要： A power amplifier module includes a power amplifier including a GaAs bipolar transistor having a collector, a base abutting the collector, and an emitter, the collector having a doping concentration of at least about 3×1016 cm−3 at a junction with the base, the collector also having at least a first grading in which doping concentration increases away from the base; and an RF transmission line driven by the power amplifier, the RF transmission line including a conductive layer and finish plating on the conductive layer, the finish plating including a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer, the diffusion barrier layer including nickel and having a thickness that is less than about the skin depth of nickel at 0.9 GHz. Other embodiments of the module are provided along with related methods and components thereof.

摘要翻译： 功率放大器模块包括功率放大器，其包括具有集电极的GaAs双极晶体管，邻接集电极的基极和发射极，该集电极在与基极的连接处具有至少约3×1016cm-3的掺杂浓度，所述收集器还具有至少第一分级，其中掺杂浓度从所述基底增加; 以及由功率放大器驱动的RF传输线，RF传输线包括在导电层上的导电层和精整电镀，精加工镀层包括金层，接近金层的钯层和靠近金层的扩散阻挡层钯层，扩散阻挡层包括镍，并且其厚度小于0.9GHz处的镍的趋肤深度。模块的其他实施例与其相关方法和组件一起提供。

24.

发明申请
SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF 有权
标题翻译：半导体封装及其制造方法

公开(公告)号：US20120326305A1

公开(公告)日：2012-12-27

申请号：US13242462

申请日：2011-09-23

申请人： Liang-Yi Hung , Yu Cheng Pai , Ming Chen Sun , Chun Hsien Lin

发明人： Liang-Yi Hung , Yu Cheng Pai , Ming Chen Sun , Chun Hsien Lin

IPC分类号： H01L23/498 , H01L21/56

CPC分类号： H01L21/568 , H01L21/6835 , H01L23/3128 , H01L24/48 , H01L24/97 , H01L2221/68345 , H01L2224/16245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/85416 , H01L2224/85439 , H01L2224/85444 , H01L2924/00014 , H01L2924/181 , H01L2224/45099 , H01L2924/00012

摘要： A semiconductor package includes: a dielectric layer having opposing first and second surfaces and side surfaces; a copper wiring layer disposed on the first surface of the dielectric layer and having extension pads; a surface processing layer disposed on the wiring layer; a semiconductor chip disposed on the wiring layer and electrically connected to the surface processing layer; and an encapsulant disposed on the first surface of the dielectric layer for encapsulating the semiconductor chip, the wiring layer and the surface processing layer while exposing the second surface of the dielectric layer. Further, vias are disposed between the side surfaces of the dielectric layer and the encapsulant such that the extension pads are exposed from the vias so as for solder balls to be disposed thereon. Due to improved electrical connection between the copper and solder materials, the electrical connection quality of the package is improved.

摘要翻译： 半导体封装包括：具有相对的第一和第二表面和侧表面的电介质层; 设置在所述电介质层的所述第一表面上并具有延伸焊盘的铜布线层; 布置在所述布线层上的表面处理层; 设置在所述布线层上并与表面处理层电连接的半导体芯片; 以及设置在电介质层的第一表面上的密封剂，用于在暴露电介质层的第二表面的同时封装半导体芯片，布线层和表面处理层。此外，通孔设置在电介质层的侧表面和密封剂之间，使得延伸垫从通孔露出，以便焊球位于其上。由于铜和焊料材料之间的电连接改善，封装的电连接质量得到改善。

25.

发明申请
WIRE BOND PAD SYSTEM AND METHOD 有权
标题翻译：电线键盘系统和方法

公开(公告)号：US20120222892A1

公开(公告)日：2012-09-06

申请号：US13040127

申请日：2011-03-03

申请人： Weimin Sun , Peter J. Zampardi , Hongxiao Shao

发明人： Weimin Sun , Peter J. Zampardi , Hongxiao Shao

IPC分类号： H05K1/09 , H05K3/00 , C25D7/00 , C25D5/02 , C25D19/00

CPC分类号： H01L23/66 , C25D5/022 , C25D5/12 , C25D7/0607 , C25D17/00 , H01L23/49838 , H01L23/49866 , H01L24/03 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L2223/6605 , H01L2223/6611 , H01L2224/03424 , H01L2224/03462 , H01L2224/03464 , H01L2224/04042 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05644 , H01L2224/45144 , H01L2224/45147 , H01L2224/48095 , H01L2224/48229 , H01L2224/48644 , H01L2224/48655 , H01L2224/48664 , H01L2224/49111 , H01L2224/85205 , H01L2224/85411 , H01L2224/85416 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/85464 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/1421 , H01L2924/15747 , H01L2924/2064 , H05K1/0243 , H05K1/09 , H05K1/111 , H05K3/10 , H05K3/244 , H05K3/3452 , H05K2203/049 , H05K2203/0597 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099

摘要： To reduce the RF losses associated with high RF loss plating, such as, for example, Ni/Pd/Au plating, the solder mask is reconfigured to prevent the edges and sidewalls of the wire-bond areas from being plated in some embodiments. Leaving the edges and sidewalls of the wire-bond areas free from high RF loss plating, such as Ni/Pd/Au plating, provides a path for the RF current to flow around the high resistivity material, which reduces the RF signal loss associated with the high resistivity plating material.

摘要翻译： 为了减少与诸如例如Ni / Pd / Au电镀的高RF损耗电镀相关联的RF损耗，在一些实施例中，重新配置焊接掩模以防止引线接合区域的边缘和侧壁被电镀。离开没有高RF损耗电镀（例如Ni / Pd / Au电镀）的引线键合区域的边缘和侧壁提供了用于RF电流围绕高电阻率材料流动的路径，这降低了与高电阻率电镀材料。

26.

发明公开
SEMICONDUCTOR PACKAGE 审中-公开

公开(公告)号：US20230215791A1

公开(公告)日：2023-07-06

申请号：US17933272

申请日：2022-09-19

申请人： Samsung Electronics Co., Ltd.

发明人： Jinmo Kwon

IPC分类号： H01L23/498 , H01L23/31 , H01L23/00

CPC分类号： H01L23/49822 , H01L23/3128 , H01L23/49827 , H01L23/49816 , H01L24/48 , H01L24/16 , H01L23/49838 , H01L2224/48227 , H01L2224/16227 , H01L2224/45144 , H01L2224/45139 , H01L2224/45116 , H01L2224/45124 , H01L2224/45147 , H01L24/45 , H01L2224/32225 , H01L24/32 , H01L2224/05647 , H01L2224/05624 , H01L2224/05639 , H01L2224/05611 , H01L2224/05644 , H01L2224/05655 , H01L2224/05616 , H01L2224/05666 , H01L24/05 , H01L2224/13111 , H01L2224/13109 , H01L2224/13113 , H01L2224/1312 , H01L2224/13147 , H01L2224/13139 , H01L2224/13118 , H01L2224/13116 , H01L24/13 , H01L2224/85411 , H01L2224/85416 , H01L2224/85455 , H01L2224/85444 , H01L24/85 , H01L2224/81411 , H01L2224/81416 , H01L2224/81455 , H01L2224/81444 , H01L24/81 , H01L2224/73265 , H01L24/73

摘要： A semiconductor package includes: a substrate including an insulating layer, a plurality of pads on the insulating layer, a surface protective layer covering the insulating layer and having first through-holes exposing at least a portion of the insulating layer and second through-holes exposing at least a portion of each of the plurality of pads, a plurality of first dummy patterns extending from the plurality of pads to the first through-holes, and a plurality of second dummy patterns extending from the first through-holes to an edge of the insulating layer; a semiconductor chip on the substrate and including connection terminals electrically connected to the plurality of pads exposed through the second through-holes; and an encapsulant encapsulating at least a portion of the semiconductor chip and filling the first through-holes, wherein a separation distance between the first through-holes is greater than a separation distance between the second through-holes.