公开(公告)号：US20140328105A1

公开(公告)日：2014-11-06

申请号：US14334653

申请日：2014-07-17

Applicant: SanDisk 3D LLC

Inventor： Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

IPC: G11C5/06

CPC classification number: G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

Abstract: Apparatus, methods, and systems are provided for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled thereto; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks, are formed using a sidewall defined process, and have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern that allows a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Other aspects are disclosed.

Abstract translation: 为三维存储器的存储器层布局提供了装置，方法和系统。 存储层包括多个存储器阵列块; 耦合到其上的多个存储线; 以及用于将存储器层耦合到三维存储器中的其它存储器层的多个zia接触区域。 存储器线从存储器阵列块延伸，使用侧壁限定的工艺形成，并且半间距尺寸小于形成存储器线的光刻工具的标称最小特征尺寸能力。 zia接触区域的尺寸约为存储器线的半间距尺寸的四倍。 存储线被布置成允许单个存储器线与单个zia接触区域相交并且为其它zia接触区域提供在其它存储器线路之间的区域的图案。 公开其他方面。

公开(公告)号：US08773898B2

公开(公告)日：2014-07-08

申请号：US13890622

申请日：2013-05-09

Applicant: SanDisk 3D LLC

Inventor： Tyler J. Thorp ,  Roy E. Scheuerlein

IPC: G11C13/00

CPC classification number: G11C7/12 ,  G11C7/065 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0061 ,  G11C13/0069

Abstract: A method is provided for programming a memory cell having a first terminal coupled to a word line and a second terminal coupled to a bit line. During a first predetermined time interval, the word line is switched from a first standby voltage to a first voltage, the bit line is switched from a second standby voltage to a predetermined voltage, and a voltage drop across the first and second terminals is a safe voltage that does not program the memory cell. During a second predetermined time interval, the word line is switched from the first voltage to a second voltage, and a voltage drop across the first and second terminals is a programming voltage that is sufficient to program the memory cell. Numerous other aspects are provided.

Abstract translation: 提供了一种用于对具有耦合到字线的第一端子和耦合到位线的第二端子的存储单元进行编程的方法。 在第一预定时间间隔期间，字线从第一备用电压切换到第一电压，位线从第二待机电压切换到预定电压，并且跨第一和第二端子的电压降是安全的 不对存储单元进行编程的电压。 在第二预定时间间隔期间，字线从第一电压切换到第二电压，并且跨越第一和第二端子的电压降是足以编程存储器单元的编程电压。 提供了许多其他方面。

公开(公告)号：US20140078851A1

公开(公告)日：2014-03-20

申请号：US14089715

申请日：2013-11-25

Applicant: Sandisk 3D LLC

Inventor： Roy E. Scheuerlein

IPC: G11C13/00

CPC classification number: G11C13/0033 ,  G11C5/025 ,  G11C8/08 ,  G11C13/0002 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/2454 ,  H01L27/2463 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/165 ,  H01L45/1683

Abstract: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

公开(公告)号：US08565015B2

公开(公告)日：2013-10-22

申请号：US13765394

申请日：2013-02-12

Applicant: SanDisk 3D LLC

Inventor： Tyler J. Thorp ,  Roy E. Scheuerlein

IPC: G11C11/00

CPC classification number: G11C13/0004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0092

Abstract: Methods of programming two terminal memory cells are provided. A method includes: (a) reading information of a memory page including first, second, and nth memory cells, the information including first, second, and nth program pulse tuning instructions; (b) creating a first program pulse in accordance with the first program pulse tuning instructions to program the first memory cell; (c) locking the first memory cell from further programming pulses; (d) creating a second program pulse in accordance with the second program pulse tuning instructions to program the second memory cell; (e) locking the second memory cell from further programming pulses; and (f) creating an nth program pulse in accordance with the nth program pulse tuning instructions to program the nth memory cell.

Abstract translation: 提供了编程两个终端存储单元的方法。 一种方法包括：（a）读取包括第一，第二和第n存储器单元的存储器页的信息，该信息包括第一，第二和第N编程脉冲调谐指令; （b）根据第一编程脉冲调谐指令产生第一编程脉冲以对第一存储单元进行编程; （c）锁定所述第一存储器单元以进一步编程脉冲; （d）根据第二编程脉冲调谐指令产生第二编程脉冲以编程第二存储单元; （e）锁定所述第二存储器单元以进一步编程脉冲; 和（f）根据第n个编程脉冲调谐指令产生第n个编程脉冲以对第n个存储单元进行编程。

公开(公告)号：US20130264675A1

公开(公告)日：2013-10-10

申请号：US13911294

申请日：2013-06-06

Applicant: SanDisk 3D LLC

Inventor： Roy E. Scheuerlein

IPC: H01L21/48 ,  H01L23/538 ,  H01L27/10

CPC classification number: H01L21/48 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76817 ,  H01L23/5384 ,  H01L27/10 ,  H01L27/101 ,  H01L2221/1021 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory layer in a three-dimensional memory array is provided. The memory layer includes a plurality of memory lines and vias formed by a damascene process using an imprint lithography template having a plurality of depths, wherein at least one depth corresponds to the memory lines and wherein at least one depth corresponds to the vias, and a plurality of memory cells operatively coupled to the memory lines. Numerous other aspects are disclosed.

Abstract translation: 提供三维存储器阵列中的存储器层。 存储层包括多个存储线和通过使用具有多个深度的压印光刻模板的镶嵌工艺形成的通孔，其中至少一个深度对应于存储器线，并且其中至少一个深度对应于通孔，并且 多个可操作地耦合到存储器线的存储单元。 公开了许多其他方面。

公开(公告)号：US20130148421A1

公开(公告)日：2013-06-13

申请号：US13765394

申请日：2013-02-12

Applicant: SanDisk 3D LLC

Inventor： Tyler J. Thorp ,  Roy E. Scheuerlein

IPC: G11C13/00

CPC classification number: G11C13/0004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0092

Abstract: Methods of programming two terminal memory cells are provided. A method includes: (a) reading information of a memory page including first, second, and nth memory cells, the information including first, second, and nth program pulse tuning instructions; (b) creating a first program pulse in accordance with the first program pulse tuning instructions to program the first memory cell; (c) locking the first memory cell from further programming pulses; (d) creating a second program pulse in accordance with the second program pulse tuning instructions to program the second memory cell; (e) locking the second memory cell from further programming pulses; and (f) creating an nth program pulse in accordance with the nth program pulse tuning instructions to program the nth memory cell.

Abstract translation: 提供了编程两个终端存储单元的方法。 一种方法包括：（a）读取包括第一，第二和第n存储器单元的存储器页的信息，该信息包括第一，第二和第N编程脉冲调谐指令; （b）根据第一编程脉冲调谐指令产生第一编程脉冲以对第一存储单元进行编程; （c）锁定所述第一存储器单元以进一步编程脉冲; （d）根据第二编程脉冲调谐指令产生第二编程脉冲以编程第二存储单元; （e）锁定所述第二存储器单元以进一步编程脉冲; 和（f）根据第n个编程脉冲调谐指令产生第n个编程脉冲以对第n个存储单元进行编程。

公开(公告)号：US20130135925A1

公开(公告)日：2013-05-30

申请号：US13750917

申请日：2013-01-25

Applicant: SANDISK 3D LLC

Inventor： Roy E. Scheuerlein

IPC: G11C11/21

CPC classification number: G11C11/21 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481

Abstract: A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.

Abstract translation: 具有包括二极管和相变材料的存储单元的存储器阵列通过将所有未选择的存储单元维持在反向偏置状态来可靠地编程。 因此，泄漏低，并且确保没有未选择的存储器单元受到干扰。 为了在顺序写入期间避免干扰未选择的存储单元，在选择新的位线和字线之前，先前选择的字线和位线被带到其未选择的电压。 改进的电流镜结构控制相变材料的状态切换。

公开(公告)号：US20130119338A1

公开(公告)日：2013-05-16

申请号：US13734517

申请日：2013-01-04

Applicant: SanDisk 3D LLC

Inventor： Xiaoyu Yang ,  Roy E. Scheuerlein ,  Feng Li ,  Albert T. Meeks

IPC: H01L45/00

CPC classification number: H01L45/12 ,  G11C17/00 ,  G11C17/16 ,  H01L23/5252 ,  H01L27/101 ,  H01L45/04 ,  H01L45/146 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory cell is provided that includes a diode and a resistance-switching material layer coupled in series with the diode. The resistance-switching material layer: (a) includes a material from the family consisting of XvOw, wherein X represents an element from the family consisting of Hf and Zr, and wherein the subscripts v and w have non-zero values that form a stable compound, and (b) has a thickness between 20 and 65 angstroms. Other aspects are also provided.

Abstract translation: 提供存储单元，其包括与二极管串联耦合的二极管和电阻切换材料层。 电阻切换材料层：（a）包括由XvOw组成的族的材料，其中X表示由Hf和Zr组成的族的元素，并且其中下标v和w具有形成稳定的非零值 化合物，（b）的厚度为20至65埃。 还提供其他方面。

公开(公告)号：USRE46435E1

公开(公告)日：2017-06-13

申请号：US14291415

申请日：2014-05-30

Applicant: SanDisk 3D LLC

Inventor： Roy E. Scheuerlein ,  Christopher J. Petti

IPC: G11C5/02 ,  G11C8/08 ,  G11C16/04

CPC classification number: G03F7/2022 ,  B82Y10/00 ,  H01L27/0207 ,  H01L27/1021 ,  H01L27/112 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085

Abstract: A nonvolatile memory device includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern. The nonvolatile memory cells may be pillar shaped non-volatile memory cells which can be patterned using triple or quadruple exposure lithography or by using a self-assembling layer.

公开(公告)号：US09472301B2

公开(公告)日：2016-10-18

申请号：US14804126

申请日：2015-07-20

Applicant: SanDisk 3D LLC

Inventor： Abhijit Bandyopadhyay ,  Tanmay Kumar ,  Scott Brad Herner ,  Christopher J. Petti ,  Roy E. Scheuerlein

IPC: G11C17/16 ,  G11C17/18 ,  G11C11/56 ,  H01L27/112 ,  H01L27/102 ,  H01L45/00 ,  H01L29/861 ,  H01L27/24

CPC classification number: G11C17/165 ,  G11C11/5692 ,  G11C17/18 ,  H01L27/1021 ,  H01L27/11206 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2481 ,  H01L29/8615 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

Abstract: A method of programming a memory cell is provided. The memory cell includes a memory element having a first conductive material layer, a first dielectric material layer above the first conductive material layer, a second conductive material layer above the first dielectric material layer, a second dielectric material layer above the second conductive material layer, and a third conductive material layer above the second dielectric material layer. One or both of the first and second conductive material layers comprises a stack of a metal material layer and a highly doped semiconductor material layer. The memory cell has a first memory state upon fabrication corresponding to a first read current. The method includes applying a first programming pulse to the memory cell with a first current limit. The first programming pulse programs the memory cell to a second memory state that corresponds to a second read current greater than the first read current.

Abstract translation: 提供了一种编程存储器单元的方法。 存储单元包括具有第一导电材料层，在第一导电材料层上方的第一介电材料层，第一介电材料层上方的第二导电材料层，第二导电材料层上方的第二介电材料层的存储元件， 以及在第二介电材料层上方的第三导电材料层。 第一和第二导电材料层中的一个或两个包括金属材料层和高掺杂半导体材料层的叠层。 存储单元在制造时具有对应于第一读取电流的第一存储器状态。 该方法包括以第一电流限制对存储器单元施加第一编程脉冲。 第一编程脉冲将存储器单元编程为对应于大于第一读取电流的第二读取电流的第二存储器状态。