公开(公告)号：US20170338186A1

公开(公告)日：2017-11-23

申请号：US15669273

申请日：2017-08-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Fu-Tang Huang ,  Chun-Chi Ke

IPC: H01L23/552 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/91 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/06133 ,  H01L2224/06135 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48132 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49052 ,  H01L2224/49107 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/92165 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06537 ,  H01L2225/06568 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package is provided, including: a substrate; a first semiconductor element disposed on the substrate and having a first conductive pad grounded to the substrate; a conductive layer formed on the first semiconductor element and electrically connected to the substrate; a second semiconductor element disposed on the first semiconductor element through the conductive layer; and an encapsulant formed on the substrate and encapsulating the first and second semiconductor elements. Therefore, the first and second semiconductor elements are protected from electromagnetic interference (EMI) shielding with the conductive layer being connected to the grounding pad of the substrate. A fabrication method of the semiconductor package is also provided.

公开(公告)号：US20170287874A1

公开(公告)日：2017-10-05

申请号：US15455143

申请日：2017-03-10

Applicant: Powertech Technology Inc.

Inventor： Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin ,  Chien-Wen Huang

IPC: H01L25/065 ,  H01L23/552 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/552 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13021 ,  H01L2224/16227 ,  H01L2224/24225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/82039 ,  H01L2224/92225 ,  H01L2224/92244 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/15192 ,  H01L2924/3025

Abstract: A stacked chip package structure includes a first chip, pillar bumps, a first encapsulant, a first redistribution layer, a second chip, a second encapsulant, a second redistribution layer and a through via. The pillar bumps are disposed on a plurality of first pads of the first chip respectively. The first encapsulant encapsulates the first chip and exposes the pillar bumps. The first redistribution layer is disposed on the first encapsulant and electrically connects the first chip. The second chip is disposed on the first redistribution layer. The second encapsulant encapsulates the second chip. The second redistribution layer is disposed on the second encapsulant and electrically coupled to the second chip. The through via penetrates the second encapsulant and electrically connects the first redistribution layer and the second redistribution layer.

公开(公告)号：US20170271231A1

公开(公告)日：2017-09-21

申请号：US15252158

申请日：2016-08-30

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Masaji IWAMOTO

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/552 ,  H01L23/29

CPC classification number: H01L23/3135 ,  H01L21/56 ,  H01L23/29 ,  H01L23/3121 ,  H01L23/373 ,  H01L23/552 ,  H01L23/562 ,  H01L23/564 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/15313 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00

Abstract: According to one embodiment, a semiconductor device includes a substrate, semiconductor chips mounted on the substrate, a sealing resin layer that seals the semiconductor chips, and a film covering at least an upper surface of the sealing resin layer, the film made from a material selected from the group consisting of zinc, aluminum, manganese, alloys thereof, metal oxides, metal nitrides, and metal oxynitrides.

公开(公告)号：US09754874B2

公开(公告)日：2017-09-05

申请号：US14062924

申请日：2013-10-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsiao-Tsung Yen ,  Cheng-Wei Luo

IPC: H01L21/8234 ,  H01L21/8244 ,  H01L23/522 ,  H01L21/822 ,  H01L23/66 ,  H01L27/06 ,  H01L25/065

CPC classification number: H01L23/5227 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/66 ,  H01L25/065 ,  H01L25/0657 ,  H01L27/0694 ,  H01L2223/6622 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductive capacitive structure including a first substrate, a first conductive line over the first substrate, a first shielding layer over the first substrate and a second substrate over the first substrate.

公开(公告)号：US20170243858A1

公开(公告)日：2017-08-24

申请号：US15588690

申请日：2017-05-07

Applicant: MEDIATEK INC.

Inventor： Che-Ya Chou ,  Kun-Ting Hung ,  Chia-Hao Yang ,  Nan-Cheng Chen

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/85005 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06537 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/142 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/83005 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/48247

Abstract: A semiconductor package is provided. The semiconductor package includes a carrier substrate having opposite first surface and second surface, and a chip stack disposed on the first surface of the carrier substrate. The chip stack includes a first semiconductor die, a second semiconductor die, and an interposer between the first semiconductor die and the second semiconductor die. The interposer transmits signals between the first semiconductor die and the second semiconductor die.

公开(公告)号：US09741687B2

公开(公告)日：2017-08-22

申请号：US15151722

申请日：2016-05-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Nan Shih

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L25/065 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L25/00 ,  H01L25/16

CPC classification number: H01L25/0652 ,  H01L21/76805 ,  H01L23/481 ,  H01L23/5223 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/11 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a first substrate including a semiconductor material, an active device at a surface of the first substrate, and a first interconnect structure over the first substrate, wherein the first tier is free from passive devices therein. The second tier includes a second substrate bonded to and in contact with the first interconnect structure, and a second interconnect structure over the second substrate, wherein metal lines in the second interconnect structure are electrically coupled to the first interconnect structure. The second tier further includes a plurality of through-vias penetrating through the second substrate, wherein the plurality of through-vias lands on metal pads in a top metal layer of the first interconnect structure, and a passive device in the second interconnect structure.

公开(公告)号：US09673179B1

公开(公告)日：2017-06-06

申请号：US15214565

申请日：2016-07-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andreas Huber ,  Harald Huels ,  Stefano S. Oggioni ,  Thomas Strach ,  Thomas-Michael Winkel

IPC: H01L25/065 ,  H01L23/498

CPC classification number: H05K1/183 ,  H01L23/49838 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06537 ,  H01L2225/06548 ,  H05K1/0219 ,  H05K1/115 ,  H05K1/144 ,  H05K1/181 ,  H05K3/0097 ,  H05K3/18 ,  H05K3/34 ,  H05K3/4697 ,  H05K2201/049 ,  H05K2201/10015 ,  H05K2201/10106

Abstract: The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.

公开(公告)号：US09660609B2

公开(公告)日：2017-05-23

申请号：US15204391

申请日：2016-07-07

Applicant: SKYWORKS SOLUTIONS, INC.

Inventor： Russ Alan Reisner ,  John C. Baldwin

IPC: H01L23/31 ,  H03H9/05 ,  H01L23/552 ,  H01L25/065 ,  H01L23/66 ,  H01L23/498 ,  H03H9/46 ,  H04B1/04 ,  H04B1/16

CPC classification number: H03H9/0566 ,  H01L23/3114 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/66 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/16 ,  H01L2223/6688 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83851 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06555 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/1421 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/19105 ,  H03H9/46 ,  H03H9/706 ,  H03H9/725 ,  H04B1/04 ,  H04B1/16 ,  H04B1/48

Abstract: Devices and method related to stacked duplexers. In some embodiments, an assembly may include a first wafer-level packaging (WLP) device having a radio-frequency (RF) shield. The assembly may also include a second WLP device having an RF shield, the second WLP device positioned over the first WLP device such that the RF shield of the second WLP device is electrically connected to the RF shield of the first WLP device.

公开(公告)号：US20170133323A1

公开(公告)日：2017-05-11

申请号：US15415462

申请日：2017-01-25

Applicant: Semtech Corporation

Inventor： Kok Khoon Ho ,  Satyamoorthi Chinnusamy

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L25/00 ,  H01L23/48 ,  H01L21/48 ,  H01L21/78 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/56 ,  H01L21/78 ,  H01L23/13 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/433 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/17 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05575 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/13013 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16113 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/1713 ,  H01L2224/17181 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/80 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10322 ,  H01L2924/10324 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/3025 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01046 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/81

Abstract: A semiconductor device has a first substrate. A conductive layer is formed over the first substrate. A first cavity is formed through the first substrate and extending to the conductive layer. A first semiconductor die including a plurality of first interconnect structures is disposed in the first cavity. A second substrate is disposed over the first substrate. A second cavity is formed through second substrate. A second semiconductor die including a plurality of second interconnect structures is disposed in the second cavity. A discrete device or third semiconductor die is disposed over the second semiconductor die. A plurality of third interconnect structures is formed between the second substrate and discrete device or third semiconductor die. The first, second, and third interconnect structures are reflowed simultaneously. An encapsulant is deposited over and around the first semiconductor die, the second semiconductor die, and the discrete device or third semiconductor die.

公开(公告)号：US20170110383A1

公开(公告)日：2017-04-20

申请号：US15395027

申请日：2016-12-30

Applicant: SanDisk Information Technology (Shanghai) Co. Ltd.

Inventor： Dacheng Huang ,  Ye Bai ,  Kaiyou Qian ,  Chin-Tien Chiu

IPC: H01L23/31 ,  H01L25/00 ,  H01L23/552 ,  H01L25/065 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/3135 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/552 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: A semiconductor device is disclosed including material for absorbing EMI and/or RFI. The device includes a substrate, one or more semiconductor die, and molding compound around the one or more semiconductor die. The material for absorbing EMI and/or RFI may be provided within or on a solder mask layer on the substrate, or within a dielectric core of the substrate. The device may further include EMI/RFI-absorbing material around the molding compound and in contact with the EMI/RFI-absorbing material on the substrate to completely enclose the one or more semiconductor die in EMI/RFI-absorbing material.