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91.发明授权Method of manufacturing semiconductor device and method of manufacturing electronic device including an adhesive layer on a support member 有权制造半导体器件的方法和制造在支撑部件上具有粘合剂层的电子器件的方法公开(公告)号：US09312151B2
公开(公告)日：2016-04-12
申请号：US13749159
申请日：2013-01-24
申请人： FUJITSU LIMITED
发明人： Shinya Sasaki , Yoshikatsu Ishizuki , Motoaki Tani
IPC分类号： H01L21/58 , H01L23/00 , H01L21/683 , H01L23/31 , H01L21/56
CPC分类号： H01L21/568 , H01L21/561 , H01L21/6835 , H01L23/3128 , H01L24/19 , H01L24/20 , H01L24/96 , H01L2221/68318 , H01L2221/68381 , H01L2224/04105 , H01L2224/12105 , H01L2224/24195 , H01L2924/10253 , H01L2924/15787 , H01L2924/15788 , H01L2924/19105 , H01L2924/00
摘要： A method of manufacturing a semiconductor device, includes: providing a first adhesive layer on a support member; providing a film on the first adhesive layer; arranging a semiconductor element on the film; providing a resin layer on the film on which the semiconductor element is arranged, and forming a substrate including the semiconductor element and the resin layer on the film; and separating the film and the substrate from the first adhesive layer.
摘要翻译： 一种制造半导体器件的方法，包括：在支撑构件上提供第一粘合剂层; 在第一粘合剂层上提供薄膜; 在所述膜上布置半导体元件; 在其上布置半导体元件的膜上提供树脂层，并在膜上形成包括半导体元件和树脂层的基板; 以及从第一粘合剂层分离膜和基底。
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92.发明授权公开(公告)号：US09308603B2
公开(公告)日：2016-04-12
申请号：US13855719
申请日：2013-04-03
发明人： Kuo-Shu Kao , Tao-Chih Chang , Wen-Chih Chen
IPC分类号： B32B15/20 , B23K35/24 , B32B15/01 , B23K35/28 , B23K35/30 , H01L23/495 , H01L23/00 , H01L23/373 , H01L25/065
CPC分类号： B23K35/24 , B23K35/282 , B23K35/3013 , B23K35/302 , B32B15/01 , B32B15/018 , H01L23/3735 , H01L23/49513 , H01L23/49582 , H01L24/03 , H01L24/05 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/83 , H01L25/0657 , H01L2224/0345 , H01L2224/04026 , H01L2224/05647 , H01L2224/05655 , H01L2224/2612 , H01L2224/27826 , H01L2224/291 , H01L2224/29118 , H01L2224/29561 , H01L2224/29565 , H01L2224/29582 , H01L2224/29583 , H01L2224/29639 , H01L2224/29644 , H01L2224/29647 , H01L2224/29663 , H01L2224/29664 , H01L2224/29669 , H01L2224/29673 , H01L2224/29676 , H01L2224/29678 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/32503 , H01L2224/32507 , H01L2224/83007 , H01L2224/8309 , H01L2224/83101 , H01L2224/83203 , H01L2224/83447 , H01L2224/83455 , H01L2224/83815 , H01L2924/10253 , H01L2924/10272 , H01L2924/1033 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/15747 , H01L2924/15787 , Y10T428/12792 , H01L2924/00015 , H01L2924/00014 , H01L2924/014 , H01L2924/0105 , H01L2924/01013 , H01L2924/01029 , H01L2924/01076 , H01L2924/00012 , H01L2924/00
摘要： A solder and a solder joint structure formed by the solder are provided. The solder includes a zinc-based material, a copper film, and a noble metal film. The copper film completely covers the surface of the zinc-based material. The noble metal film completely covers the copper film. The solder joint structure includes a zinc-based material and an intermetallic layer. The intermetallic layer consists of zinc and noble metal and completely covers the surface of the zinc-based material.
摘要翻译： 提供由焊料形成的焊料和焊点结构。 焊料包括锌基材料，铜膜和贵金属膜。 铜膜完全覆盖锌基材料的表面。 贵金属膜完全覆盖铜膜。 焊接结构包括锌基材料和金属间化合物层。 金属间层由锌和贵金属组成，并完全覆盖锌基材料的表面。
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公开(公告)号：US09305808B2
公开(公告)日：2016-04-05
申请号：US14713222
申请日：2015-05-15
发明人： Chung-Yu Lu , Hsien-Pin Hu , Hsiao-Tsung Yen , Tzuan-Horng Liu , Shih-Wen Huang , Shang-Yun Hou , Shin-Puu Jeng
IPC分类号： H01L21/00 , H01L21/48 , H01L25/04 , H01L25/00 , H01L25/065 , H01L23/00 , H01L23/498
CPC分类号： H01L21/4853 , H01L23/3142 , H01L23/49811 , H01L23/49816 , H01L23/49838 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/04 , H01L25/0652 , H01L25/0655 , H01L25/50 , H01L2224/13083 , H01L2224/13147 , H01L2224/13155 , H01L2224/16055 , H01L2224/16057 , H01L2224/16058 , H01L2224/16137 , H01L2224/16227 , H01L2224/16237 , H01L2224/16238 , H01L2224/1701 , H01L2224/73204 , H01L2224/81191 , H01L2224/81193 , H01L2224/814 , H01L2924/0002 , H01L2924/15192 , H01L2924/15787 , H01L2924/15788 , H01L2924/351 , H01L2924/00 , H01L2924/014
摘要： Methods and apparatus for forming a semiconductor device package on an interposer using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, where a micro-bump is used as a vertical connection between a die and the interposer, and a micro-bump line is used as a horizontal connection for signal transmission between different dies above the interposer. The micro-bump lines may be formed at the same time as the formation of the micro-bumps with little or no additional cost.
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公开(公告)号：US20160093585A1
公开(公告)日：2016-03-31
申请号：US14963273
申请日：2015-12-09
发明人： Julien Sylvestre
CPC分类号： H01L24/17 , H01L21/50 , H01L21/563 , H01L22/14 , H01L23/3135 , H01L23/49811 , H01L23/49816 , H01L24/03 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2224/0381 , H01L2224/0401 , H01L2224/1184 , H01L2224/13016 , H01L2224/13023 , H01L2224/13082 , H01L2224/13116 , H01L2224/13147 , H01L2224/16225 , H01L2224/16238 , H01L2224/17517 , H01L2224/29286 , H01L2224/29387 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81013 , H01L2224/81024 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/81203 , H01L2224/81805 , H01L2224/81815 , H01L2224/81907 , H01L2224/83855 , H01L2224/92125 , H01L2924/01029 , H01L2924/01322 , H01L2924/014 , H01L2924/15311 , H01L2924/15787 , H01L2924/16251 , H01L2924/182 , H01L2924/3701 , H01L2924/00 , H01L2924/11
摘要： An assembly of a semiconductor chip having pads to a substrate having pads aligned to receive the semiconductor chip is provided, whereby at least one of the semiconductor chip pads and substrate pads include solder bumps. The solder bumps are deformed against the substrate pads and the semiconductor chip pads, whereby an underfill material is applied to fill the gap between the semiconductor chip and substrate. The underfill material does not penetrate between the deformed solder bumps, the semiconductor chip pads, and the substrate pads. At least one of the solder bumps have not been melted or reflowed to make a metallurgical bond between the semiconductor chip pads and the substrate pads, and at least another one of the solder bumps have been melted or reflowed to make a metallurgical bond between the semiconductor chip pads and the substrate pads.
摘要翻译： 提供具有衬垫的半导体芯片的组件，该衬底具有对准接收半导体芯片的焊盘，由此至少一个半导体芯片焊盘和衬底焊盘包括焊料凸块。 焊料凸起相对于衬底焊盘和半导体芯片焊盘变形，由此施加底部填充材料以填充半导体芯片和衬底之间的间隙。 底部填充材料不会渗透在变形的焊料凸块，半导体芯片焊盘和衬底焊盘之间。 焊料凸起中的至少一个没有被熔化或回流以在半导体芯片焊盘和衬底焊盘之间形成冶金结合，并且至少另一个焊料凸点已被熔化或回流以在半导体之间形成冶金结合 芯片焊盘和衬底焊盘。
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公开(公告)号：US20160093339A1
公开(公告)日：2016-03-31
申请号：US14962734
申请日：2015-12-08
申请人： Invensas Corporation
IPC分类号： G11C5/02 , G11C8/18 , G11C8/10 , H01L25/065 , G11C8/06
CPC分类号： G11C5/02 , G11C5/04 , G11C5/06 , G11C5/063 , G11C8/06 , G11C8/10 , G11C8/18 , H01L23/13 , H01L23/3128 , H01L23/36 , H01L23/49816 , H01L23/49827 , H01L24/16 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/92 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/02375 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/06135 , H01L2224/06165 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/45014 , H01L2224/48145 , H01L2224/48227 , H01L2224/4824 , H01L2224/49175 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/73265 , H01L2224/9202 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06558 , H01L2225/06562 , H01L2225/06589 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/1431 , H01L2924/1434 , H01L2924/1436 , H01L2924/1438 , H01L2924/1443 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/1579 , H01L2924/181 , H01L2924/18161 , H01L2924/19041 , H01L2924/19105 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane.
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公开(公告)号：US20160087179A1
公开(公告)日：2016-03-24
申请号：US14952294
申请日：2015-11-25
申请人： Michael A. TISCHLER
发明人： Michael A. TISCHLER
CPC分类号： H01L33/62 , H01L21/6836 , H01L21/78 , H01L23/544 , H01L24/05 , H01L24/06 , H01L24/27 , H01L24/29 , H01L24/81 , H01L24/83 , H01L25/0657 , H01L33/0095 , H01L33/50 , H01L33/505 , H01L2221/68327 , H01L2221/68336 , H01L2223/54426 , H01L2224/0401 , H01L2224/04026 , H01L2224/05624 , H01L2224/05638 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/0568 , H01L2224/05686 , H01L2224/06102 , H01L2224/13144 , H01L2224/13147 , H01L2224/27003 , H01L2224/27436 , H01L2224/29082 , H01L2224/2929 , H01L2224/29298 , H01L2224/32227 , H01L2224/73104 , H01L2224/80001 , H01L2224/83191 , H01L2224/83203 , H01L2224/83385 , H01L2224/83851 , H01L2224/94 , H01L2225/06513 , H01L2924/07811 , H01L2924/12041 , H01L2924/12042 , H01L2924/15787 , H01L2924/181 , H01L2933/0033 , H01L2933/0041 , H01L2933/0066 , H01L2924/00 , H01L2924/00015 , H01L2924/01014
摘要： In accordance with certain embodiments, semiconductor dies are at least partially coated with a conductive adhesive prior to singulation and subsequently bonded to a substrate having electrical traces thereon.
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97.发明授权公开(公告)号：US09293431B2
公开(公告)日：2016-03-22
申请号：US14551874
申请日：2014-11-24
IPC分类号： H01L23/48 , H01L23/00 , H01L25/065 , H01L23/64 , H01L25/16 , H01L25/00 , H01L21/768
CPC分类号： H01L24/09 , H01L21/76898 , H01L23/481 , H01L23/64 , H01L24/08 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/80 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L25/16 , H01L25/50 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/08145 , H01L2224/13022 , H01L2224/13124 , H01L2224/13147 , H01L2224/24011 , H01L2224/24051 , H01L2224/24105 , H01L2224/24145 , H01L2224/80896 , H01L2224/81 , H01L2224/821 , H01L2224/9202 , H01L2224/9212 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06565 , H01L2924/00014 , H01L2924/01322 , H01L2924/1205 , H01L2924/1305 , H01L2924/13091 , H01L2924/15787 , H01L2924/00 , H01L2224/82 , H05K3/4661 , H01L2224/05552 , H01L2224/8203 , H01L2224/80001
摘要： The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate, the second bond pad electrically connecting to the second electrical device; a second insulation layer over the second bond pad having a top surface, the second insulation layer being bonded toward the first bond pad of the first substrate; and a through-substrate-via (“TSV”) extending from a surface opposite to the first bond pad through the first substrate and through the top surface of the second insulation layer to the second bond pad.
摘要翻译： 本公开提供了堆叠半导体器件的一个实施例。 叠层半导体器件包括第一衬底; 第一衬底上的第一接合焊盘; 第二基板，包括在其上制造的第二电气装置; 在所述第二基板上方的所述第二电气装置上的第二接合焊盘，所述第二接合焊盘电连接到所述第二电气装置; 所述第二接合焊盘上的第二绝缘层具有顶表面，所述第二绝缘层朝向所述第一基板的所述第一接合焊盘接合; 以及从第一接合焊盘相反的表面穿过第一基板延伸并穿过第二绝缘层的顶表面延伸到第二接合焊盘的贯通基板通孔（“TSV”）。
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公开(公告)号：US09293385B2
公开(公告)日：2016-03-22
申请号：US12182132
申请日：2008-07-30
IPC分类号： H01L23/31 , H01L21/56 , H01L23/00 , H01L25/10 , H01L23/495 , H01L23/498 , H01L23/538
CPC分类号： H01L23/3128 , H01L21/561 , H01L23/49548 , H01L23/49816 , H01L23/5389 , H01L24/48 , H01L24/73 , H01L24/97 , H01L25/105 , H01L2224/04042 , H01L2224/16 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/8592 , H01L2224/97 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2225/1088 , H01L2924/00011 , H01L2924/00014 , H01L2924/01027 , H01L2924/01033 , H01L2924/14 , H01L2924/15331 , H01L2924/15787 , H01L2924/181 , H01L2924/1815 , H01L2224/85 , H01L2224/83 , H01L2924/00012 , H01L2924/00 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit package system includes: providing an internal device; encapsulating the internal device with an encapsulation having an outer surface; and forming a redistribution line having connection points on the outer surface of the encapsulation.
摘要翻译： 集成电路封装系统包括：提供内部装置; 用具有外表面的封装封装内部装置; 并且在所述封装的外表面上形成具有连接点的再分配线。
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公开(公告)号：US09293338B2
公开(公告)日：2016-03-22
申请号：US14074687
申请日：2013-11-07
发明人： Chang-Ming Lin , Yu-Juan Tao
IPC分类号： H01L21/285 , H01L23/00 , H01L21/28 , H01L23/36 , H01L23/367 , H01L23/498 , H01L23/31
CPC分类号： H01L23/485 , H01L21/28 , H01L21/28587 , H01L23/3121 , H01L23/3142 , H01L23/3192 , H01L23/36 , H01L23/3675 , H01L23/3677 , H01L23/48 , H01L23/482 , H01L23/49838 , H01L23/49861 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/83 , H01L24/94 , H01L2224/02311 , H01L2224/02313 , H01L2224/02331 , H01L2224/0239 , H01L2224/0345 , H01L2224/0361 , H01L2224/03612 , H01L2224/03614 , H01L2224/03912 , H01L2224/0401 , H01L2224/05025 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/06102 , H01L2224/1132 , H01L2224/11462 , H01L2224/1147 , H01L2224/1182 , H01L2224/11825 , H01L2224/11849 , H01L2224/119 , H01L2224/11903 , H01L2224/1191 , H01L2224/13024 , H01L2224/13076 , H01L2224/13082 , H01L2224/13084 , H01L2224/131 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/13541 , H01L2224/13562 , H01L2224/1357 , H01L2224/13582 , H01L2224/136 , H01L2224/13609 , H01L2224/13611 , H01L2224/13639 , H01L2224/13644 , H01L2224/13655 , H01L2224/14051 , H01L2224/16055 , H01L2224/16058 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/17106 , H01L2224/17519 , H01L2224/73204 , H01L2224/81191 , H01L2224/81424 , H01L2224/81447 , H01L2224/831 , H01L2224/92 , H01L2224/92125 , H01L2224/94 , H01L2924/12042 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/2064 , H01L2924/20641 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2224/03 , H01L2224/11 , H01L2224/0231 , H01L21/304 , H01L21/78 , H01L2224/81 , H01L2924/00
摘要： A semiconductor packaging method is provided. The method includes providing a semiconductor substrate. The semiconductor substrate has a first surface and a second surface, and an electroplating seed layer on the first surface of the semiconductor substrate. The method also includes forming a plurality of columnar electrodes over the electroplating seed layer, where the columnar electrodes include first columnar electrodes and second columnar electrodes. Further, the method includes forming a diffusion barrier layer over the first columnar electrodes and the second columnar electrodes, forming a plurality of first solder balls over the diffusion barrier layer on the first columnar electrodes. The method also includes providing a packaging substrate having solder terminals corresponding to the first solder balls, and mounting the semiconductor substrate onto the packaging substrate in a flipped position, such that the first solder balls are connected with the solder terminals.
摘要翻译： 提供半导体封装方法。 该方法包括提供半导体衬底。 半导体衬底具有第一表面和第二表面，以及在半导体衬底的第一表面上的电镀籽晶层。 该方法还包括在电镀种子层上形成多个柱状电极，其中柱状电极包括第一柱状电极和第二柱状电极。 此外，该方法包括在第一柱状电极和第二柱状电极上形成扩散阻挡层，在第一柱状电极上的扩散阻挡层上形成多个第一焊球。 该方法还包括提供具有对应于第一焊球的焊接端子的封装基板，并将半导体基板安装在翻转位置的封装基板上，使得第一焊球与焊接端子连接。
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公开(公告)号：US20160079221A1
公开(公告)日：2016-03-17
申请号：US14785314
申请日：2013-07-04
IPC分类号： H01L25/18 , H01L23/31 , H01L23/48 , H01L21/48 , H01L23/367 , H01L23/495 , H01L23/522 , H01L21/56 , H01L23/50
CPC分类号： H01L25/18 , H01L21/4825 , H01L21/565 , H01L23/051 , H01L23/3107 , H01L23/3121 , H01L23/3675 , H01L23/4334 , H01L23/481 , H01L23/49541 , H01L23/49562 , H01L23/49575 , H01L23/49589 , H01L23/50 , H01L23/5228 , H01L24/36 , H01L24/37 , H01L24/40 , H01L25/07 , H01L2224/05553 , H01L2224/0603 , H01L2224/37011 , H01L2224/40137 , H01L2224/48137 , H01L2224/48139 , H01L2224/48247 , H01L2224/48472 , H01L2224/73221 , H01L2224/83801 , H01L2224/84205 , H01L2224/84801 , H01L2224/8485 , H01L2924/00014 , H01L2924/13055 , H01L2924/13091 , H01L2924/15787 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/37099
摘要： Fixing a semiconductor element to a substrate, electrically connecting signal and main terminals to the semiconductor element, a terminal aggregate includes a frame portion, the signal terminal, the main terminal, which has a larger width than the signal terminal, and a dummy terminal, and forming a to-be-encapsulated body in which the substrate, the semiconductor element, and the terminal aggregate are integrated, mounting the to-be-encapsulated body on a lower mold half such that a plurality of blocks formed in the lower mold half are meshed with the signal, main, and dummy terminals with no space left therebetween after the mounting, placing a bottom surface of an upper mold half on top surfaces of the plurality of blocks, and top surfaces of the signal, main, and dummy terminals to form a cavity for the substrate and the semiconductor element, and performing molding by injecting mold resin into the cavity are included.
摘要翻译： 将半导体元件固定到基板上，将信号和主端子电连接到半导体元件，端子集合体包括具有比信号端子宽的宽度的框架部分，信号端子，主端子以及虚拟端子， 并且形成将所述基板，所述半导体元件和所述端子集合体一体化的被封装体，将所述被封装体安装在下半模上，使得形成在所述下半模中的多个块 与信号，主和虚拟端子啮合，安装后没有留下空间，将上半模的底面放置在多个块的顶表面上，信号，主和虚拟端子的顶表面 以形成用于基板和半导体元件的空腔，并且包括通过将模制树脂注入空腔来进行模制。
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