公开(公告)号：US20180040573A1

公开(公告)日：2018-02-08

申请号：US15786623

申请日：2017-10-18

Applicant: Infineon Technologies AG

Inventor： FRANK PUESCHNER ,  JENS POHL

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49855 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/50 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/86 ,  H01L24/92 ,  H01L2224/1134 ,  H01L2224/11464 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1624 ,  H01L2224/16257 ,  H01L2224/1626 ,  H01L2224/26175 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/27618 ,  H01L2224/27622 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/29386 ,  H01L2224/2939 ,  H01L2224/29393 ,  H01L2224/32013 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/753 ,  H01L2224/7598 ,  H01L2224/81 ,  H01L2224/81903 ,  H01L2224/8314 ,  H01L2224/83203 ,  H01L2224/83208 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/01012 ,  H01L2924/0103 ,  H01L2924/0104 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2924/01006 ,  H01L2224/83

Abstract: A method may include providing a chip carrier having a chip supporting region to support a chip, and a chip contacting region having at least one contact pad, the chip carrier being thinner in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region. A disposing of the chip, having at least one contact protrusion, over the chip carrier, such that the at least one contact protrusion is arranged over the at least one contact pad may be included. In addition, a pressing of the chip against the chip carrier such that the at least one contact protrusion extends at least partially into the chip contacting region and is electrically contacted to the at least one contact pad may be included.

公开(公告)号：US20170069592A1

公开(公告)日：2017-03-09

申请号：US15122926

申请日：2015-03-31

Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.

Inventor： Ryo MATSUBAYASHI

IPC: H01L23/00 ,  B23K20/02 ,  B23K1/00

CPC classification number: H01L24/75 ,  B23K1/0016 ,  B23K20/023 ,  B23K20/233 ,  B23K2101/42 ,  H01L21/52 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/32225 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75305 ,  H01L2224/7531 ,  H01L2224/75312 ,  H01L2224/75502 ,  H01L2224/7565 ,  H01L2224/75824 ,  H01L2224/83203 ,  H01L2224/83208 ,  H01L2224/8384 ,  H01L2924/10158 ,  H01L2924/00014

Abstract: Provided is transferring members having a plate-like shape used in baking a metal particle paste of an assembled body formed by arranging an electronic part on a substrate with the metal particle paste interposed therebetween by applying pressure to the assembled body and by heating the assembled body, the transferring members being configured to sandwich the assembled body in baking the metal particle paste, wherein the transferring members are made of a material having thermal conductivity which falls within a range of from 1 to 200 W/(m k) and Vickers hardness which falls within a range of from 180 to 2300 kgf/mm2.With such a configuration, it is possible to provide a transferring member for being used in a method of manufacturing a bonded body which can suppress the lowering of bonding property between a substrate and an electronic part and which can prevent the remarkable lowering of productivity of a bonded body.

Abstract translation: 通过这样的结构，可以提供一种用于制造接合体的方法中的转印部件，其能够抑制基板和电子部件之间的接合性能的降低，并且可以防止显着降低生产率 粘结体。

公开(公告)号：US20130043015A1

公开(公告)日：2013-02-21

申请号：US13212494

申请日：2011-08-18

Applicant: Ivan Straznicky ,  Peter Robert Lawrence Kaiser ,  Steven Drennan ,  Marc-Jason Renaud ,  Georges Francis Marquis

Inventor： Ivan Straznicky ,  Peter Robert Lawrence Kaiser ,  Steven Drennan ,  Marc-Jason Renaud ,  Georges Francis Marquis

IPC: F28F7/00 ,  B23P15/26

CPC classification number: H01L23/373 ,  H01L23/36 ,  H01L23/42 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/27334 ,  H01L2224/29109 ,  H01L2224/32245 ,  H01L2224/83024 ,  H01L2224/8314 ,  H01L2224/83191 ,  H01L2224/83208 ,  H01L2224/8321 ,  H01L2224/83815 ,  H01L2924/10253 ,  Y10T29/49393 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method includes preparing a bonding surface of a heat dissipating member, applying flux to the bonding surface of the heat dissipating member, and removing excess flux from the bonding surface so that minimal flux is provided. The method also includes preparing a die surface of an electronic device package, applying flux to the die surface, and removing excess flux from the die surface so that minimal flux is provided. The method further includes positioning a preform solder component on the die surface, positioning the heat dissipating member over the die surface and the preform solder component such that the flux layer of the bonding surface is in contact with the preform solder component, and reflowing the solder component using a reflow oven. A heat spreader is also described for use in the process.

Abstract translation: 一种方法包括制备散热构件的接合表面，将助焊剂施加到散热构件的接合表面，以及从接合表面去除过量的焊剂，从而提供最小的通量。 该方法还包括制备电子器件封装的管芯表面，向管芯表面施加焊剂，以及从管芯表面去除多余的焊剂，从而提供最小的焊剂。 该方法还包括将预制件焊料组分定位在模具表面上，将散热构件定位在模具表面上和预成型件焊料部件上，使得接合表面的焊剂层与预成型件焊料部件接触，并且回流焊料 组件使用回流炉。 散热器也被描述为用于该过程。

公开(公告)号：US20180358320A1

公开(公告)日：2018-12-13

申请号：US15996744

申请日：2018-06-04

Applicant: FUJITSU LIMITED

Inventor： Kimio Nakamura ,  NAOKI ISHIKAWA ,  Hiroshi Kobayashi ,  Shuichi Takeuchi

IPC: H01L23/00

CPC classification number: H01L24/73 ,  H01L24/05 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13144 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81205 ,  H01L2224/81208 ,  H01L2224/8183 ,  H01L2224/83192 ,  H01L2224/83208 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2924/3511

Abstract: An electronic device includes a first electronic part that includes a first terminal, a second electronic part disposed to be opposed to the first electronic part, the second electronic part that includes a second terminal including a first end part in contact with the first terminal and a second end part located on an outside of the first terminal, and an adhesive disposed between the first electronic part and the second electronic part, the adhesive maintaining the contact between the first terminal and the first end part by bonding the first electronic part and the second electronic part to each other.

公开(公告)号：US20180072923A1

公开(公告)日：2018-03-15

申请号：US15704456

申请日：2017-09-14

Applicant: E I DU PONT DE NEMOURS AND COMPANY

Inventor： Yumi Matsuura

IPC: C09J9/02 ,  C09J101/28 ,  C09J11/04 ,  C09J11/06 ,  C09J5/06 ,  H01L23/00 ,  B23K35/02

CPC classification number: C09J9/02 ,  B23K35/025 ,  C08K2003/0806 ,  C08K2201/001 ,  C08L1/28 ,  C09J5/06 ,  C09J11/04 ,  C09J11/06 ,  C09J101/28 ,  C09J2401/00 ,  C09J2433/00 ,  H01L24/05 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/2732 ,  H01L2224/27332 ,  H01L2224/2747 ,  H01L2224/2929 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29369 ,  H01L2224/29373 ,  H01L2224/32151 ,  H01L2224/32227 ,  H01L2224/83048 ,  H01L2224/83097 ,  H01L2224/83191 ,  H01L2224/83208 ,  H01L2224/83851 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/13072 ,  H01L2924/14 ,  C08L1/284 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/06

Abstract: The present invention relates to a conductive paste for bonding comprising 100 parts by weight of the metal powder, 5 to 20 parts by weight of a solvent, and 0.05 to 3 parts by weight of a polymer, wherein the polymer comprises a first polymer and a second polymer, wherein the molecular weight (Mw) of the first polymer is 5,000 to 95,000, and the molecular weight (Mw) of the second polymer is 100,000 to 300,000.

公开(公告)号：US09824983B2

公开(公告)日：2017-11-21

申请号：US15232815

申请日：2016-08-10

Applicant: Infineon Technologies AG

Inventor： Frank Pueschner ,  Jens Pohl

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49855 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/50 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/1134 ,  H01L2224/11464 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1624 ,  H01L2224/16257 ,  H01L2224/1626 ,  H01L2224/26175 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/27618 ,  H01L2224/27622 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/29386 ,  H01L2224/2939 ,  H01L2224/29393 ,  H01L2224/32013 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/753 ,  H01L2224/7598 ,  H01L2224/81 ,  H01L2224/81903 ,  H01L2224/8314 ,  H01L2224/83203 ,  H01L2224/83208 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/01012 ,  H01L2924/0103 ,  H01L2924/0104 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2924/01006 ,  H01L2224/83

Abstract: According to various embodiments, a chip carrier may include: a chip supporting region configured to support a chip; a chip contacting region including at least one contact pad for electrically contacting the chip; wherein the chip carrier is thinned in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region.

公开(公告)号：US20100190293A1

公开(公告)日：2010-07-29

申请号：US12670127

申请日：2008-07-18

Applicant: Jun Maeda ,  Keiko Tanaka ,  Osamu Yamazaki

Inventor： Jun Maeda ,  Keiko Tanaka ,  Osamu Yamazaki

IPC: H01L21/50

CPC classification number: H01L21/6836 ,  H01L21/304 ,  H01L21/563 ,  H01L21/78 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L24/90 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81903 ,  H01L2224/83191 ,  H01L2224/83208 ,  H01L2224/838 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/351 ,  H01L2924/00015 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/0401

Abstract: The present invention has been achieved reflecting such situation, and its object is to provide a manufacturing method of a semiconductor device capable of continuously performing the mounting process which applies a so-called DBG process and a flip chip bonding method, and can contribute to simplify the manufacturing process and to improve the reliability with no void in the product. The manufacturing method of a semiconductor device according to the present invention comprises: laminating a surface protective sheet to a circuit surface side of a wafer formed with grooves which divide each circuit wherein an adhesive film is adhered on the circuit surface of the wafer; reducing the thickness of the wafer and finally dividing the wafer into individual chips by grinding a back face of the wafer; picking up individual chips together with the adhesive film; die-bonding said individual chip to predetermined position of a chip mounting substrate via said adhesive film; fixing the chip to the chip mounting substrate by heating the die-bonded chip having the adhesive film; and applying a static pressure larger than an ambient pressure by 0.05 MPa or more to a stacked body including the adhesive film one or more times, at any point between adhering the wafer to the adhesive film and fixing the chip to the chip mounting substrate.

Abstract translation: 已经实现了本发明，反映了这种情况，其目的在于提供能够连续进行所谓的DBG处理和倒装芯片接合方法的安装工序的半导体装置的制造方法，能够有助于简化 制造过程中提高产品的可靠性，无空白。 根据本发明的半导体器件的制造方法包括：将表面保护片层压到形成有凹槽的晶片的电路表面侧，所述晶片将每个电路分开，其中粘合剂膜粘附在晶片的电路表面上; 减小晶片的厚度，最后通过研磨晶片的背面将晶片分成单独的芯片; 用粘合膜拾取单个芯片; 将所述单个芯片经由所述粘合膜将所述芯片贴合到芯片安装基板的预定位置; 通过加热具有粘合膜的芯片接合芯片将芯片固定到芯片安装基板; 并且在将晶片粘附到粘合剂膜上并将芯片固定到芯片安装基板之间的任何点处，将包括粘合剂膜的层叠体施加大于0.05MPa或更大的环境压力的静态压力一次或多次。

公开(公告)号：US20170271295A1

公开(公告)日：2017-09-21

申请号：US15514524

申请日：2015-09-17

Applicant: OSRAM Oplo Semiconductors GmbH

Inventor： Andreas Ploessl

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/15

CPC classification number: H01L24/29 ,  H01L23/15 ,  H01L23/49513 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/15 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L33/40 ,  H01L33/62 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05678 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1141 ,  H01L2224/11436 ,  H01L2224/13294 ,  H01L2224/13339 ,  H01L2224/13347 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/2741 ,  H01L2224/27436 ,  H01L2224/29083 ,  H01L2224/29084 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/29173 ,  H01L2224/29178 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81207 ,  H01L2224/81208 ,  H01L2224/81469 ,  H01L2224/81473 ,  H01L2224/81478 ,  H01L2224/8184 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83207 ,  H01L2224/83208 ,  H01L2224/83359 ,  H01L2224/83439 ,  H01L2224/83447 ,  H01L2224/83469 ,  H01L2224/83473 ,  H01L2224/83478 ,  H01L2224/8384 ,  H01L2924/00015 ,  H01L2924/1033 ,  H01L2924/10349 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/13014 ,  H01L2924/13064 ,  H01L2924/15724 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2224/05639 ,  H01L2924/00012

Abstract: An electronic device and a method for producing an electronic device are disclosed. In an embodiment the electronic device includes a first component and a second component and a sinter layer connecting the first component to the second component, the sinter layer comprising a first metal, wherein at least one of the components comprises at least one contact layer which is arranged in direct contact with the sinter layer, which comprises a second metal different from the first metal and which is free of gold.

公开(公告)号：US20160111395A1

公开(公告)日：2016-04-21

申请号：US14870064

申请日：2015-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Alexander Heinrich

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L25/0655 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/4827 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/544 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L24/97 ,  H01L25/50 ,  H01L2221/68354 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04026 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/05687 ,  H01L2224/06183 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/27334 ,  H01L2224/27436 ,  H01L2224/2908 ,  H01L2224/291 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/2916 ,  H01L2224/29166 ,  H01L2224/29171 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/75102 ,  H01L2224/75251 ,  H01L2224/75265 ,  H01L2224/75303 ,  H01L2224/75753 ,  H01L2224/7598 ,  H01L2224/83002 ,  H01L2224/83005 ,  H01L2224/83007 ,  H01L2224/83024 ,  H01L2224/83055 ,  H01L2224/83065 ,  H01L2224/83075 ,  H01L2224/8309 ,  H01L2224/83091 ,  H01L2224/83092 ,  H01L2224/83101 ,  H01L2224/83127 ,  H01L2224/83132 ,  H01L2224/83143 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83208 ,  H01L2224/83222 ,  H01L2224/83385 ,  H01L2224/83424 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8346 ,  H01L2224/83464 ,  H01L2224/83466 ,  H01L2224/83469 ,  H01L2224/8381 ,  H01L2224/83815 ,  H01L2224/8382 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/83907 ,  H01L2224/83986 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2924/01015 ,  H01L2924/04941 ,  H01L2924/0496 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15157 ,  H01L2924/157 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01028 ,  H01L2924/01026 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01074 ,  H01L2924/01024 ,  H01L2924/01023 ,  H01L2924/01027

Abstract: A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

Abstract translation: 形成芯片组件的方法可以包括在载体中形成多个空腔; 该方法还可以包括在每个空腔中设置管芯附着液体; 在芯片安装液体上布置多个芯片，每个芯片包括设置在后侧金属化之后的后侧金属化和后侧互连材料，其中后侧互连材料面向载体; 蒸发管芯附着液体; 并且在蒸发模具附着液体之后，将多个芯片固定到载体上。

公开(公告)号：US09214446B2

公开(公告)日：2015-12-15

申请号：US13422656

申请日：2012-03-16

Applicant: Kaoru Yoda

Inventor： Kaoru Yoda

IPC: B29C65/00 ,  H01L23/00

CPC classification number: H01L24/83 ,  H01L24/32 ,  H01L2224/29019 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32059 ,  H01L2224/32238 ,  H01L2224/7592 ,  H01L2224/81192 ,  H01L2224/81444 ,  H01L2224/81895 ,  H01L2224/83099 ,  H01L2224/83193 ,  H01L2224/83208 ,  H01L2224/83385 ,  H01L2224/83444 ,  H01L2224/83895 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12043 ,  Y10T156/1039 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The present invention is directed to provide a method of manufacturing an optical module in which optical devices are optically aligned with high precision regardless of elastic return of bonding bumps. The invention provides a method of manufacturing an optical module including the steps of forming bumps for bonding made of metal on a substrate, and bonding a second optical device on the bonding bumps by applying a load so that the bumps for bonding are deformed only by a predetermined amount from a position where a first optical device and the second optical device are optically coupled most efficiently and, after that, releasing the load.

Abstract translation: 本发明旨在提供一种制造光学模块的方法，其中光学器件以高精度光学对准，而与接合凸块的弹性返回无关。 本发明提供了一种制造光学模块的方法，包括以下步骤：在基板上形成用于接合金属的凸块，并且通过施加负载将第二光学装置接合在接合凸块上，使得用于接合的凸块仅通过 从第一光学装置和第二光学装置最有效地光耦合的位置起预定量，然后释放负载。