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公开(公告)号：US11315892B2
公开(公告)日：2022-04-26
申请号：US16059468
申请日：2018-08-09
发明人： Roman Roth , Frank Hille , Hans-Joachim Schulze
IPC分类号： H01L23/00 , H01L23/532 , H01L21/768
摘要： A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device includes a first load terminal structure, a second load terminal structure, and a semiconductor structure electrically coupled to each load terminal structure and configured to carry a load current. The first load terminal structure includes a conductive layer in contact with the semiconductor structure, a bonding block configured to be contacted by at least one bond wire and to receive at least a part of the load current from the at least one bond wire and/or the conductive layer, a support block having a hardness greater than the hardness of the conductive layer and the bonding block. The bonding block is mounted on the conductive layer via the support block, and a zone is arranged within the conductive layer and/or the bonding block, the zone exhibiting nitrogen atoms.
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公开(公告)号：US10978418B2
公开(公告)日：2021-04-13
申请号：US16572626
申请日：2019-09-17
发明人： Joachim Mahler , Michael Bauer , Jochen Dangelmaier , Reimund Engl , Johann Gatterbauer , Frank Hille , Michael Huettinger , Werner Kanert , Heinrich Koerner , Brigitte Ruehle , Francisco Javier Santos Rodriguez , Antonio Vellei
IPC分类号： H01L23/00 , H01L23/31 , H01L23/29 , H01L21/02 , H01L23/495
摘要： A method of forming an electrical contact and a method of forming a chip package are provided. The methods may include arranging a metal contact structure including a non-noble metal and electrically contacting the chip, arranging a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.
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公开(公告)号：US10475743B2
公开(公告)日：2019-11-12
申请号：US15458366
申请日：2017-03-14
发明人： Frank Hille , Ravi Keshav Joshi , Michael Fugger , Oliver Humbel , Thomas Laska , Matthias Mueller , Roman Roth , Carsten Schaeffer , Hans-Joachim Schulze , Holger Schulze , Juergen Steinbrenner , Frank Umbach
IPC分类号： H01L21/768 , H01L23/532 , H01L23/522 , H01L23/528
摘要： According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a semiconductor body and a metal adhesion and barrier structure between the metal structure and the semiconductor body. The metal adhesion and barrier structure includes a first layer having titanium and tungsten, and a second layer having titanium, tungsten, and nitrogen on the first layer having titanium and tungsten.
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4.发明申请公开(公告)号：US20180226471A1
公开(公告)日：2018-08-09
申请号：US15885340
申请日：2018-01-31
发明人： Frank Hille , Andre Brockmeier , Francisco Javier Santos Rodriguez , Daniel Schloegl , Hans-Joachim Schulze
IPC分类号： H01L29/06 , H01L21/02 , H01L21/225 , H01L21/78 , H01L21/306
CPC分类号： H01L29/0638 , H01L21/02378 , H01L21/02381 , H01L21/0243 , H01L21/02634 , H01L21/02658 , H01L21/2252 , H01L21/30608 , H01L21/78 , H01L21/7806 , H01L29/0619 , H01L29/0661 , H01L29/66333 , H01L29/66363 , H01L29/7395 , H01L29/74 , H01L29/7802 , H01L29/861
摘要： Epitaxy troughs are formed in a semiconductor substrate, wherein a matrix section of the semiconductor substrate laterally separates the epitaxy troughs and comprises a first semiconductor material. Crystalline epitaxy regions of a second semiconductor material are formed in the epitaxy troughs, wherein the second semiconductor material differs from the first semiconductor material in at least one of porosity, impurity content or defect density. From the epitaxy regions at least main body portions of semiconductor bodies of the semiconductor devices are formed.
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5.发明申请公开(公告)号：US20170338169A1
公开(公告)日：2017-11-23
申请号：US15600857
申请日：2017-05-22
发明人： Joachim Mahler , Michael Bauer , Jochen Dangelmaier , Reimund Engl , Johann Gatterbauer , Frank Hille , Michael Huettinger , Werner Kanert , Heinrich Koerner , Brigitte Ruehle , Francisco Javier Santos Rodriguez , Antonio Vellei
IPC分类号： H01L23/495 , H01L23/31 , H01L23/29 , H01L21/02 , H01L23/00
CPC分类号： H01L24/48 , H01L21/02164 , H01L21/0217 , H01L21/02266 , H01L21/02271 , H01L21/02274 , H01L21/0228 , H01L21/02288 , H01L23/293 , H01L23/3107 , H01L23/3135 , H01L23/3142 , H01L23/4952 , H01L23/49582 , H01L24/03 , H01L24/05 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/73 , H01L24/83 , H01L24/85 , H01L2224/0346 , H01L2224/03826 , H01L2224/03827 , H01L2224/03831 , H01L2224/04042 , H01L2224/05073 , H01L2224/05139 , H01L2224/05147 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05657 , H01L2224/05664 , H01L2224/05666 , H01L2224/05681 , H01L2224/05684 , H01L2224/2919 , H01L2224/32245 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/45572 , H01L2224/45573 , H01L2224/45611 , H01L2224/45618 , H01L2224/45639 , H01L2224/45644 , H01L2224/45649 , H01L2224/45655 , H01L2224/45657 , H01L2224/45664 , H01L2224/45666 , H01L2224/4567 , H01L2224/45671 , H01L2224/45672 , H01L2224/4568 , H01L2224/45686 , H01L2224/4569 , H01L2224/45693 , H01L2224/48091 , H01L2224/48106 , H01L2224/4813 , H01L2224/48247 , H01L2224/4846 , H01L2224/48463 , H01L2224/48465 , H01L2224/4847 , H01L2224/48507 , H01L2224/73265 , H01L2224/85205 , H01L2224/85375 , H01L2224/85801 , H01L2224/8592 , H01L2924/00014 , H01L2924/0132 , H01L2924/10253 , H01L2924/181 , H01L2924/00012 , H01L2924/00015 , H01L2924/01046 , H01L2224/45669 , H01L2924/01029 , H01L2924/01028 , H01L2924/01056 , H01L2924/00 , H01L2224/43848
摘要： In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.
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6.发明申请Method of Manufacturing a Reduced Free-Charge Carrier Lifetime Semiconductor Structure 有权制造减少自由载流子寿命半导体结构的方法公开(公告)号：US20140213022A1
公开(公告)日：2014-07-31
申请号：US14228330
申请日：2014-03-28
IPC分类号： H01L29/66
CPC分类号： H01L29/66348 , H01L27/0611 , H01L29/167 , H01L29/32 , H01L29/7397
摘要： A method of manufacturing a reduced free-charge carrier lifetime semiconductor structure includes forming a plurality of transistor gate structures in trenches arranged in a semiconductor substrate, forming a body region between adjacent ones of the transistor gate structures and forming an end-of-range irradiation region between adjacent ones of the transistor gate structures, the end-of-range irradiation region having a plurality of vacancies.
摘要翻译： 一种制造减小的自由电荷载流子寿命半导体结构的方法包括在布置在半导体衬底中的沟槽中形成多个晶体管栅极结构，在相邻的晶体管栅极结构之间形成体区，并形成距离范围 所述晶体管栅极结构中的相邻晶体管栅极结构之间的区域，所述端部范围照射区域具有多个空位。
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公开(公告)号：US20240213343A1
公开(公告)日：2024-06-27
申请号：US18533872
申请日：2023-12-08
发明人： Roland Dietmüller , Andreas Korzenietz , Bernd Bitnar , Wolfgang Wagner , Philip Christoph Brandt , Frank Hille , Volodymyr Komarnitskyy , Frank Pfirsch , Franz Josef Niedernostheide , Marc Probst
IPC分类号： H01L29/423 , H01L29/40 , H01L29/66 , H01L29/739 , H01L29/78
CPC分类号： H01L29/42364 , H01L29/401 , H01L29/4236 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/7813
摘要： A power semiconductor device includes a first region in an active region of a semiconductor body and including first trenches each having a first trench electrode electrically connected to a gate terminal and a first trench insulator. A second region includes second trenches each having a second trench electrode electrically connected to the gate terminal and a second trench insulator. At least one of the following applies: a minimal thickness of each second trench insulator amounts to at least 120% of a corresponding minimal thickness of each first trench insulator; an average thickness of the second trench insulators amounts to at least 120% of an average thickness of the first trench insulators; a trench bottom thickness of each second trench insulator amounts to at least 120% of a corresponding trench bottom thickness of each first trench insulator; a minimal breakdown voltage of each second trench insulator amounts to at least 120% of a minimal breakdown voltage of each first trench insulator.
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公开(公告)号：US20240194778A1
公开(公告)日：2024-06-13
申请号：US18080427
申请日：2022-12-13
发明人： Michael Hell , Rudolf Elpelt , Frank Hille , Caspar Leendertz , Armin Willmeroth
IPC分类号： H01L29/78 , H01L21/265 , H01L21/266 , H01L29/06 , H01L29/16
CPC分类号： H01L29/7811 , H01L21/26513 , H01L21/266 , H01L29/0634 , H01L29/0696 , H01L29/1608
摘要： A semiconductor device includes: a semiconductor substrate having an active device region that includes a plurality of device cells and a termination region between the active device region and an edge of the semiconductor substrate; a field termination structure in the termination region and including a continuous region of a first conductivity type and a plurality of rings of the first conductivity type in the continuous region and having a higher average doping concentration than the continuous region; and a charge balance structure in the active device region and including interleaved columns of the first conductivity type and of a second conductivity type opposite the first conductivity type. The charge balance structure extends into the termination region below the field termination structure such that at least an outermost one of the columns of the first conductivity type is connected to the continuous region of the field termination structure.
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公开(公告)号：US20200013722A1
公开(公告)日：2020-01-09
申请号：US16577316
申请日：2019-09-20
发明人： Frank Hille , Ravi Keshav Joshi , Michael Fugger , Oliver Humbel , Thomas Laska , Matthias Müller , Roman Roth , Carsten Schaeffer , Hans-Joachim Schulze , Holger Schulze , Juergen Steinbrenner , Frank Umbach
IPC分类号： H01L23/532 , H01L21/768 , H01L23/522 , H01L23/528
摘要： According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a silicon carbide semiconductor body and a metal adhesion and barrier structure between the metal structure and the silicon carbide semiconductor body. The metal adhesion and barrier structure includes a layer comprising titanium and tungsten.
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公开(公告)号：US10461056B2
公开(公告)日：2019-10-29
申请号：US15600857
申请日：2017-05-22
发明人： Joachim Mahler , Michael Bauer , Jochen Dangelmaier , Reimund Engl , Johann Gatterbauer , Frank Hille , Michael Huettinger , Werner Kanert , Heinrich Koerner , Brigitte Ruehle , Francisco Javier Santos Rodriguez , Antonio Vellei
IPC分类号： H01L23/00 , H01L23/31 , H01L23/29 , H01L21/02 , H01L23/495
摘要： In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.
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