公开(公告)号：US10132696B2

公开(公告)日：2018-11-20

申请号：US14329389

申请日：2014-07-11

Applicant: Infineon Technologies AG

Inventor： Andreas Kiep ,  Holger Ruething ,  Frank Wolter

IPC: G01R31/02 ,  G01K7/01 ,  H01L27/06

Abstract: A semiconductor die includes a discrete semiconductor device and at least one diode. The temperature of the discrete semiconductor device is determined by measuring a first forward voltage drop of the at least one diode under a first test condition, measuring a second forward voltage drop of the at least one diode under a second test condition and estimating the temperature of the discrete semiconductor device based on the difference between the first and second forward voltage drop measurements.

公开(公告)号：US20160011058A1

公开(公告)日：2016-01-14

申请号：US14329389

申请日：2014-07-11

Applicant: Infineon Technologies AG

Inventor： Andreas Kiep ,  Holger Ruething ,  Frank Wolter

IPC: G01K7/01 ,  H01L29/739 ,  H01L27/06

CPC classification number: G01K7/01 ,  H01L27/0629 ,  H01L27/0664

Abstract: A semiconductor die includes a discrete semiconductor device and at least one diode. The temperature of the discrete semiconductor device is determined by measuring a first forward voltage drop of the at least one diode under a first test condition, measuring a second forward voltage drop of the at least one diode under a second test condition and estimating the temperature of the discrete semiconductor device based on the difference between the first and second forward voltage drop measurements.

Abstract translation: 半导体管芯包括分立半导体器件和至少一个二极管。 通过在第一测试条件下测量所述至少一个二极管的第一正向压降来测量分立半导体器件的温度，在第二测试条件下测量所述至少一个二极管的第二正向压降，并估计所述至少一个二极管的温度 基于第一和第二正向压降测量之间的差异的分立半导体器件。

公开(公告)号：US11387359B2

公开(公告)日：2022-07-12

申请号：US16713392

申请日：2019-12-13

Applicant: Infineon Technologies AG

Inventor： Oliver Humbel ,  Josef-Georg Bauer ,  Jens Brandenburg ,  Diana Car ,  Philipp Sebastian Koch ,  Angelika Koprowski ,  Sebastian Kremp ,  Thomas Kurzmann ,  Erwin Lercher ,  Holger Ruething

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/739

Abstract: A power semiconductor device having a power semiconductor transistor configuration includes: a semiconductor body having a front side coupled to a first load terminal structure, a backside coupled to a second load terminal structure, and a lateral chip edge; an active region for conducting a load current in a conducting state; and an edge termination region separating the active region and lateral chip edge. At the front-side, the edge termination region includes a protection region devoid of any metallic structure, unless the metallic structure is electrically shielded from below by a polysilicon layer that extends further towards the lateral chip edge than the metallic structure by a lateral distance of at least 20 μm. In a blocking state, the protection region accommodates a voltage change of at least 90% of a blocking voltage inside the semiconductor body in a lateral direction from the active region towards the lateral chip edge.

公开(公告)号：US10712208B2

公开(公告)日：2020-07-14

申请号：US16142824

申请日：2018-09-26

Applicant: Infineon Technologies AG

Inventor： Andreas Kiep ,  Holger Ruething ,  Frank Wolter

IPC: G01K7/01 ,  H01L27/06

Abstract: A semiconductor die includes a single power transistor or power diode, a temperature sense diode formed close enough to the single power transistor or power diode to measure an accurate temperature. The temperature sense diode comprises first and second diodes or strings of diodes. A separate integrated circuit is operable to measure first and second voltage drops of both the first and second diodes or strings of diodes using same magnitude currents, and estimate the temperature of the single power transistor or power diode based on the difference between the first and second forward voltage drop measurements. An overall pn junction area of the first diode or string of first diodes is different from an overall pn junction area of the second diode or string of second diodes.

公开(公告)号：US09543405B2

公开(公告)日：2017-01-10

申请号：US14228330

申请日：2014-03-28

Applicant: Infineon Technologies AG

Inventor： Holger Ruething ,  Hans-Joachim Schulze ,  Frank Hille ,  Frank Pfirsch

IPC: H01L29/73 ,  H01L29/66 ,  H01L29/32 ,  H01L29/739 ,  H01L27/06 ,  H01L29/167

CPC classification number: H01L29/66348 ,  H01L27/0611 ,  H01L29/167 ,  H01L29/32 ,  H01L29/7397

Abstract: A method of manufacturing a reduced free-charge carrier lifetime semiconductor structure includes forming a plurality of transistor gate structures in trenches arranged in a semiconductor substrate, forming a body region between adjacent ones of the transistor gate structures and forming an end-of-range irradiation region between adjacent ones of the transistor gate structures, the end-of-range irradiation region having a plurality of vacancies.

Abstract translation: 一种制造减小的自由电荷载流子寿命半导体结构的方法包括在布置在半导体衬底中的沟槽中形成多个晶体管栅极结构，在相邻的晶体管栅极结构之间形成体区，并形成距离范围 所述晶体管栅极结构中的相邻晶体管栅极结构之间的区域，所述端部范围照射区域具有多个空位。

公开(公告)号：US20190025132A1

公开(公告)日：2019-01-24

申请号：US16142824

申请日：2018-09-26

Applicant: Infineon Technologies AG

Inventor： Andreas Kiep ,  Holger Ruething ,  Frank Wolter

IPC: G01K7/01 ,  H01L27/06

CPC classification number: G01K7/01 ,  H01L27/0629 ,  H01L27/0664

Abstract: A semiconductor die includes a single power transistor or power diode, a temperature sense diode formed close enough to the single power transistor or power diode to measure an accurate temperature. The temperature sense diode comprises first and second diodes or strings of diodes. A separate integrated circuit is operable to measure first and second voltage drops of both the first and second diodes or strings of diodes using same magnitude currents, and estimate the temperature of the single power transistor or power diode based on the difference between the first and second forward voltage drop measurements. An overall pn junction area of the first diode or string of first diodes is different from an overall pn junction area of the second diode or string of second diodes.

公开(公告)号：US20140213022A1

公开(公告)日：2014-07-31

申请号：US14228330

申请日：2014-03-28

Applicant: Infineon Technologies AG

Inventor： Holger Ruething ,  Hans-Joachim Schulze ,  Frank Hille ,  Frank Pfirsch

IPC: H01L29/66

CPC classification number: H01L29/66348 ,  H01L27/0611 ,  H01L29/167 ,  H01L29/32 ,  H01L29/7397

Abstract: A method of manufacturing a reduced free-charge carrier lifetime semiconductor structure includes forming a plurality of transistor gate structures in trenches arranged in a semiconductor substrate, forming a body region between adjacent ones of the transistor gate structures and forming an end-of-range irradiation region between adjacent ones of the transistor gate structures, the end-of-range irradiation region having a plurality of vacancies.

Abstract translation: 一种制造减小的自由电荷载流子寿命半导体结构的方法包括在布置在半导体衬底中的沟槽中形成多个晶体管栅极结构，在相邻的晶体管栅极结构之间形成体区，并形成距离范围 所述晶体管栅极结构中的相邻晶体管栅极结构之间的区域，所述端部范围照射区域具有多个空位。