公开(公告)号：US10712208B2

公开(公告)日：2020-07-14

申请号：US16142824

申请日：2018-09-26

Applicant: Infineon Technologies AG

Inventor： Andreas Kiep ,  Holger Ruething ,  Frank Wolter

IPC: G01K7/01 ,  H01L27/06

Abstract: A semiconductor die includes a single power transistor or power diode, a temperature sense diode formed close enough to the single power transistor or power diode to measure an accurate temperature. The temperature sense diode comprises first and second diodes or strings of diodes. A separate integrated circuit is operable to measure first and second voltage drops of both the first and second diodes or strings of diodes using same magnitude currents, and estimate the temperature of the single power transistor or power diode based on the difference between the first and second forward voltage drop measurements. An overall pn junction area of the first diode or string of first diodes is different from an overall pn junction area of the second diode or string of second diodes.

公开(公告)号：US10388776B2

公开(公告)日：2019-08-20

申请号：US16189279

申请日：2018-11-13

Applicant: Infineon Technologies AG

Inventor： Maria Cotorogea ,  Frank Wolter ,  Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Yvonne Gawlina-Schmidl

IPC: H01L29/06 ,  H01L29/739 ,  H01L29/08 ,  H01L29/40 ,  H01L29/10 ,  H01L29/78 ,  H01L27/11521 ,  H01L27/105 ,  H01L27/115

Abstract: A semiconductor device includes: a drift region formed in a semiconductor substrate; a body region above the drift region; an active gate trench extending from a first main surface and into the body region and including a first electrode coupled to a gate potential; a source region formed in the body region adjacent to the gate trench and coupled to a source potential; a first body trench extending from the first main surface and into the body region and including a second electrode coupled to the source potential; and an inactive gate trench extending from the first main surface and into the body region and including a third electrode coupled to the gate potential. A conductive channel is present along the active gate trench when the gate potential is at an on-voltage, whereas no conductive channel is present along the inactive gate trench for the same gate potential condition.

公开(公告)号：US20160268177A1

公开(公告)日：2016-09-15

申请号：US15062828

申请日：2016-03-07

Applicant: Infineon Technologies AG

Inventor： Andreas Riegler ,  Angelika Koprowski ,  Mathias Plappert ,  Frank Wolter

IPC: H01L21/66 ,  H01L29/739 ,  H01L29/861 ,  H01L29/78

CPC classification number: H01L22/30 ,  H01L22/20 ,  H01L29/456 ,  H01L29/47 ,  H01L29/7393 ,  H01L29/7801

Abstract: A semiconductor arrangement is presented. The semiconductor arrangement comprises a semiconductor body, the semiconductor body including a semiconductor drift region, wherein the semiconductor drift region has dopants of a first conductivity type; a first semiconductor sense region and a second semiconductor sense region, wherein each of the first semiconductor sense region and the second semiconductor sense region is electrically connected to the semiconductor drift region and has dopants of a second conductivity type different from said first conductivity type; a first metal contact comprising a first metal material, the first metal contact being in contact with the first semiconductor sense region, wherein a transition between the first metal contact and the first semiconductor sense region forms a first metal-to-semiconductor transition; a second metal contact comprising a second metal material different from said first metal material, the second metal contact being separated from the first metal contact and in contact with the second semiconductor sense region, a transition between the second metal contact and the second semiconductor sense region forming a second metal-to-semiconductor transition different from said first metal-to-semiconductor transition; first electrical transmission means, the first electrical transmission means being arranged and configured for providing a first sense signal derived from an electrical parameter of the first metal contact to a first signal input of a sense signal processing unit; and second electrical transmission means separated from said first electrical transmission means, the second electrical transmission means being arranged and configured for providing a second sense signal derived from an electrical parameter of the second metal contact to a second signal input of said sense signal processing unit.

Abstract translation: 介绍了半导体布置。 所述半导体装置包括半导体本体，所述半导体本体包括半导体漂移区，其中所述半导体漂移区具有第一导电类型的掺杂剂; 第一半导体感测区域和第二半导体感测区域，其中第一半导体感测区域和第二半导体感测区域中的每一个电连接到半导体漂移区域，并且具有不同于所述第一导电类型的第二导电类型的掺杂剂; 第一金属触点，包括第一金属材料，所述第一金属触点与所述第一半导体感测区域接触，其中所述第一金属触点和所述第一半导体感测区域之间的转变形成第一金属对半导体转变; 包括不同于所述第一金属材料的第二金属材料的第二金属触点，所述第二金属触点与所述第一金属触点分离并与所述第二半导体感测区域接触，所述第二金属触点和所述第二半导体感测区域之间的过渡 形成不同于所述第一金属 - 半导体转变的第二金属 - 半导体转变; 第一电传输装置，第一电传输装置被布置和配置为将从第一金属触点的电参数导出的第一感测信号提供给感测信号处理单元的第一信号输入; 以及与所述第一电传输装置分离的第二电传输装置，所述第二电传输装置被布置和配置为将从所述第二金属触点的电参数导出的第二感测信号提供给所述感测信号处理单元的第二信号输入。

公开(公告)号：US11799026B2

公开(公告)日：2023-10-24

申请号：US17181408

申请日：2021-02-22

Applicant: Infineon Technologies AG

Inventor： Dethard Peters ,  Sascha Axel Baier ,  Tomas Manuel Reiter ,  Sandeep Walia ,  Frank Wolter

IPC: H01L29/78 ,  G01R31/52 ,  G01K7/16 ,  G01R31/26 ,  G01R31/27 ,  G01R31/28 ,  H01L29/16

CPC classification number: H01L29/7815 ,  G01K7/16 ,  G01R31/2628 ,  G01R31/27 ,  G01R31/2831 ,  G01R31/52 ,  H01L29/1608 ,  H01L29/7805 ,  H01L29/7813

Abstract: A semiconductor die includes: a SiC substrate; power and current sense transistors integrated in the substrate such that the current sense transistor mirrors current flow in the main power transistor; a gate terminal electrically connected to gate electrodes of both transistors; a drain terminal electrically connected to a drain region in the substrate and which is common to both transistors; a source terminal electrically connected to source and body regions of the power transistor; a dual mode sense terminal; and a doped resistor region in the substrate between the transistors. The dual mode sense terminal is electrically connected to source and body regions of the current sense transistor. The doped resistor region has a same conductivity type as the body regions of both transistors and is configured as a temperature sense resistor that electrically connects the source terminal to the dual mode sense terminal.

公开(公告)号：US10680089B2

公开(公告)日：2020-06-09

申请号：US16456895

申请日：2019-06-28

Applicant: Infineon Technologies AG

Inventor： Maria Cotorogea ,  Frank Wolter ,  Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Yvonne Gawlina-Schmidl

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/739 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L27/115 ,  H01L27/105 ,  H01L27/11521

Abstract: A semiconductor device is described in which a conductive channel is present along an active gate trench of the device when a gate potential is at an on-voltage, whereas no conductive channel is present along an inactive gate trench of the device for the same gate potential condition.

公开(公告)号：US10199291B2

公开(公告)日：2019-02-05

申请号：US15683460

申请日：2017-08-22

Applicant: Infineon Technologies AG

Inventor： Andreas Riegler ,  Angelika Koprowski ,  Mathias Plappert ,  Frank Wolter

IPC: H01L29/78 ,  H01L21/66 ,  H01L29/739 ,  H01L29/45 ,  H01L29/47

Abstract: A semiconductor arrangement is presented. The semiconductor arrangement comprises a semiconductor body, the semiconductor body including a semiconductor drift region, wherein the semiconductor drift region has dopants of a first conductivity type; a first semiconductor sense region and a second semiconductor sense region, wherein each of the first semiconductor sense region and the second semiconductor sense region is electrically connected to the semiconductor drift region and has dopants of a second conductivity type different from said first conductivity type; a first metal contact comprising a first metal material, the first metal contact being in contact with the first semiconductor sense region, wherein a transition between the first metal contact and the first semiconductor sense region forms a first metal-to-semiconductor transition; a second metal contact comprising a second metal material different from said first metal material, the second metal contact being separated from the first metal contact and in contact with the second semiconductor sense region, a transition between the second metal contact and the second semiconductor sense region forming a second metal-to-semiconductor transition different from said first metal-to-semiconductor transition; first electrical transmission means, the first electrical transmission means being arranged and configured for providing a first sense signal derived from an electrical parameter of the first metal contact to a first signal input of a sense signal processing unit; and second electrical transmission means separated from said first electrical transmission means, the second electrical transmission means being arranged and configured for providing a second sense signal derived from an electrical parameter of the second metal contact to a second signal input of said sense signal processing unit.

公开(公告)号：US20150279985A1

公开(公告)日：2015-10-01

申请号：US14228881

申请日：2014-03-28

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Johannes Georg Laven ,  Christian Jaeger ,  Frank Wolter ,  Frank Pfirsch ,  Antonio Vellei

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/40

CPC classification number: H01L29/7813 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7841

Abstract: A transistor device includes a semiconductor mesa region between first and second trenches in a semiconductor body, a body region of a first conductivity type and a source region of a second conductivity type in the semiconductor mesa region, a drift region of the second conductivity type in the semiconductor body, and a gate electrode adjacent the body region in the first trench, and dielectrically insulated from the body region by a gate dielectric. The body region separates the source region from the drift region and extends to the surface of the semiconductor mesa region adjacent the source region. The body region comprises a surface region which adjoins the surface of the semiconductor mesa region and the first trench. The surface region has a higher doping concentration than a section of the body region that separates the source region from the drift region.

Abstract translation: 晶体管器件包括在半导体主体中的第一和第二沟槽之间的半导体台面区域，半导体台面区域中的第一导电类型的主体区域和第二导电类型的源极区域，第二导电类型的漂移区域 所述半导体本体和与所述第一沟槽中的所述主体区域相邻的栅电极，并且通过栅极电介质与所述体区电介质绝缘。 体区域将源极区域与漂移区域分离并延伸到与源极区域相邻的半导体台面区域的表面。 身体区域包括邻接半导体台面区域和第一沟槽的表面的表面区域。 表面区域具有比将源极区域与漂移区域分开的体区域的部分更高的掺杂浓度。

公开(公告)号：US20140264432A1

公开(公告)日：2014-09-18

申请号：US13796287

申请日：2013-03-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Maria Cotorogea ,  Frank Wolter ,  Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Yvonne Gawlina-Schmidl

IPC: H01L29/739

CPC classification number: H01L29/7397 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/0623 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/7395 ,  H01L29/7813

Abstract: A semiconductor device in a semiconductor substrate includes a first main surface and a transistor cell. The transistor cell includes a drift region of a first conductivity type, a body region of a second conductivity type between the drift region and the first main surface, an active trench in the first main surface extending to the drift region, a source region of the first conductivity in the body region adjacent to the active trench, and a body trench at the first main surface extending to the drift region and adjacent to the body region and the drift region. The active trench includes a gate insulating layer at sidewalls and a bottom side, and a gate conductive layer. The body trench includes a conductive layer and an insulating layer at sidewalls and a bottom side, and asymmetric to a perpendicular axis of the first main surface and the body trench center.

Abstract translation: 半导体衬底中的半导体器件包括第一主表面和晶体管单元。 晶体管单元包括第一导电类型的漂移区域，漂移区域和第一主表面之间的第二导电类型的体区域，延伸到漂移区域的第一主表面中的有源沟槽，源极区域 在与主动沟槽相邻的主体区域中的第一导电性，以及在第一主表面处延伸到漂移区并且与身体区域和漂移区域相邻的主体沟槽。 有源沟槽包括在侧壁和底侧的栅极绝缘层和栅极导电层。 主体沟槽包括在侧壁和底侧的导电层和绝缘层，并且与第一主表面和体沟槽中心的垂直轴不对称。

公开(公告)号：US20230420559A1

公开(公告)日：2023-12-28

申请号：US18466039

申请日：2023-09-13

Applicant: Infineon Technologies AG

Inventor： Dethard Peters ,  Sascha Axel Baier ,  Tomas Reiter ,  Sandeep Walia ,  Frank Wolter

IPC: H01L29/78 ,  G01R31/52 ,  G01K7/16 ,  G01R31/26 ,  G01R31/27 ,  G01R31/28 ,  H01L29/16

CPC classification number: H01L29/7815 ,  G01R31/52 ,  G01K7/16 ,  G01R31/2628 ,  G01R31/27 ,  G01R31/2831 ,  H01L29/1608 ,  H01L29/7805 ,  H01L29/7813

Abstract: A semiconductor die includes: a SiC substrate; power and current sense transistors integrated in the substrate such that the current sense transistor mirrors current flow in the main power transistor; a gate terminal electrically connected to gate electrodes of both transistors; a drain terminal electrically connected to a drain region in the substrate and which is common to both transistors; a source terminal electrically connected to source regions of the power transistor; a dual mode sense terminal; and a doped resistor region in the substrate between the transistors. The dual mode sense terminal is electrically connected to source regions of the current sense transistor. The doped resistor region has an opposite conductivity type as the source regions of both transistors and is configured as a temperature sense resistor that electrically connects the source terminal to the dual mode sense terminal.

公开(公告)号：US20220271156A1

公开(公告)日：2022-08-25

申请号：US17181408

申请日：2021-02-22

Applicant: Infineon Technologies AG

Inventor： Dethard Peters ,  Sascha Axel Baier ,  Tomas Manuel Reiter ,  Sandeep Walia ,  Frank Wolter

IPC: H01L29/78 ,  H01L29/16 ,  G01R31/28 ,  G01R31/52 ,  G01R31/26 ,  G01K7/16 ,  G01R31/27

Abstract: A semiconductor die includes: a SiC substrate; power and current sense transistors integrated in the substrate such that the current sense transistor mirrors current flow in the main power transistor; a gate terminal electrically connected to gate electrodes of both transistors; a drain terminal electrically connected to a drain region in the substrate and which is common to both transistors; a source terminal electrically connected to source and body regions of the power transistor; a dual mode sense terminal; and a doped resistor region in the substrate between the transistors. The dual mode sense terminal is electrically connected to source and body regions of the current sense transistor. The doped resistor region has a same conductivity type as the body regions of both transistors and is configured as a temperature sense resistor that electrically connects the source terminal to the dual mode sense terminal.