公开(公告)号：US20220367443A1

公开(公告)日：2022-11-17

申请号：US17878990

申请日：2022-08-02

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Roman Baburske ,  Thomas Basler ,  Philip Christoph Brandt ,  Maria Cotorogea

IPC: H01L27/02 ,  H01L29/40 ,  H01L29/861 ,  H03K17/082 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/739

Abstract: A semiconductor device includes: a semiconductor region having charge carriers of a first conductivity type; a transistor cell in the semiconductor region; a semiconductor channel region in the transistor cell and having a first doping concentration of charge carriers of a second conductivity type, wherein a transition between the semiconductor channel region and the semiconductor region forms a first pn-junction; a semiconductor auxiliary region in the semiconductor region and having a second doping concentration of charge carriers of the second conductivity type. A transition between the semiconductor auxiliary region and semiconductor region forms a second pn-junction positioned deeper in the semiconductor region as compared to the first pn-junction. The semiconductor auxiliary region is positioned closest to the semiconductor channel region as compared to any other semiconductor region having charge carriers of the second conductivity type and that forms a further pn-junction with the semiconductor region.

公开(公告)号：US20200227518A1

公开(公告)日：2020-07-16

申请号：US16828665

申请日：2020-03-24

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Maria Cotorogea ,  Hans-Joachim Schulze ,  Haybat Itani ,  Erich Griebl ,  Andreas Haghofer

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L21/22 ,  H01L29/78 ,  H01L21/223 ,  H01L21/311 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

Abstract: A semiconductor device includes a plurality of first and second stripe-shaped cell trench structures formed in a semiconductor substrate and extending lengthwise in parallel with one another. Each stripe-shaped cell trench structure includes a buried electrode and an insulator layer between the buried electrode and the semiconductor substrate. A recess is formed in the insulator layer along a sidewall of one or more of the first stripe-shaped cell trench structures and vertically extends to a corresponding heavily doped contact zone. An electrically conductive material disposed in each recess contacts the corresponding buried electrode, a corresponding source zone and a corresponding heavily doped contact zone at the sidewall. Two or more of the first stripe-shaped cell trench structures are interposed between neighboring ones of the second stripe-shaped cell trench structures. Source zones alternate with portions of body zones in a lateral direction parallel to the stripe-shaped cell trench structures.

公开(公告)号：US10651165B2

公开(公告)日：2020-05-12

申请号：US14971677

申请日：2015-12-16

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Roman Baburske ,  Thomas Basler ,  Philip Christoph Brandt ,  Maria Cotorogea

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L29/739 ,  H01L29/861 ,  H01L29/40 ,  H03K17/082

Abstract: A semiconductor device includes a semiconductor region having charge carriers of a first conductivity type, a transistor cell in the semiconductor region, and a semiconductor channel region in the transistor cell and having a first doping concentration of charge carriers of a second conductivity type. A semiconductor auxiliary region in the semiconductor region has a second doping concentration of charge carriers of the second conductivity type, which is at least 30% higher than the first doping concentration. A pn-junction between the semiconductor auxiliary region and the semiconductor region is positioned as deep or deeper in the semiconductor region as a pn-junction between the semiconductor channel region and the semiconductor region. The semiconductor auxiliary region is positioned closer to the semiconductor channel region than any other semiconductor region having charge carriers of the second conductivity type and that forms a further pn-junction with the semiconductor region.

公开(公告)号：US10388776B2

公开(公告)日：2019-08-20

申请号：US16189279

申请日：2018-11-13

Applicant: Infineon Technologies AG

Inventor： Maria Cotorogea ,  Frank Wolter ,  Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Yvonne Gawlina-Schmidl

IPC: H01L29/06 ,  H01L29/739 ,  H01L29/08 ,  H01L29/40 ,  H01L29/10 ,  H01L29/78 ,  H01L27/11521 ,  H01L27/105 ,  H01L27/115

Abstract: A semiconductor device includes: a drift region formed in a semiconductor substrate; a body region above the drift region; an active gate trench extending from a first main surface and into the body region and including a first electrode coupled to a gate potential; a source region formed in the body region adjacent to the gate trench and coupled to a source potential; a first body trench extending from the first main surface and into the body region and including a second electrode coupled to the source potential; and an inactive gate trench extending from the first main surface and into the body region and including a third electrode coupled to the gate potential. A conductive channel is present along the active gate trench when the gate potential is at an on-voltage, whereas no conductive channel is present along the inactive gate trench for the same gate potential condition.

公开(公告)号：US09385228B2

公开(公告)日：2016-07-05

申请号：US14092312

申请日：2013-11-27

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Maria Cotorogea

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L29/40 ,  H01L29/08

CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7811

Abstract: A semiconductor mesa is formed in a semiconductor layer between a first cell trench structure and a second cell trench structure extending from a first surface into the semiconductor layer. An opening is formed in a capping layer formed on the first surface, wherein the opening exposes at least a portion of the semiconductor mesa. Through the opening impurities of a first conductivity type are introduced into the exposed portion of the semiconductor mesa. A recess defined by the opening is formed.

Abstract translation: 在从第一表面延伸到半导体层的第一单元沟槽结构和第二单元沟槽结构之间的半导体层中形成半导体台面。 在形成在第一表面上的覆盖层中形成开口，其中开口暴露半导体台面的至少一部分。 通过开放的第一导电类型的杂质被引入半导体台面的暴露部分。 由开口限定的凹部形成。

公开(公告)号：US20200243509A1

公开(公告)日：2020-07-30

申请号：US16844674

申请日：2020-04-09

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Roman Baburske ,  Thomas Basler ,  Philip Christoph Brandt ,  Maria Cotorogea

IPC: H01L27/02 ,  H01L29/10 ,  H03K17/082 ,  H01L29/861 ,  H01L29/40 ,  H01L29/739 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06

Abstract: A semiconductor device is operable a forward current mode and a reverse current mode and comprises a semiconductor region, and a controllable charge carrier injector, and a gate. A method includes detecting, in the reverse current mode, if the present load current in the reversed direction does not exceed a threshold value, providing a gate signal such that the gate electrode causes the charge carrier injector to induce a first charge carrier density within the semiconductor region so as to conduct a nominal load current in the reverse direction; if the present load current in the reverse direction does exceed the threshold value, operating the semiconductor device in an overload state by providing the gate signal with a voltage that causes the semiconductor region to conduct an overload current in the reverse direction, wherein the second charge carrier density is higher than the first charge carrier density.

公开(公告)号：US20190319123A1

公开(公告)日：2019-10-17

申请号：US16456895

申请日：2019-06-28

Applicant: Infineon Technologies AG

Inventor： Maria Cotorogea ,  Frank Wolter ,  Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Yvonne Gawlina-Schmidl

IPC: H01L29/739 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/78

Abstract: A semiconductor device is described in which a conductive channel is present along an active gate trench of the device when a gate potential is at an on-voltage, whereas no conductive channel is present along an inactive gate trench of the device for the same gate potential condition.

公开(公告)号：US09680005B2

公开(公告)日：2017-06-13

申请号：US14824388

申请日：2015-08-12

Applicant: Infineon Technologies AG

Inventor： Maria Cotorogea ,  Frank Wolter ,  Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Yvonne Gawlina-Schmidl

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/739 ,  H01L29/40 ,  H01L29/08 ,  H01L27/115 ,  H01L27/105 ,  H01L27/11521

CPC classification number: H01L29/7397 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/0623 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/7395 ,  H01L29/7813

Abstract: A semiconductor substrate having a first main surface and a transistor cell includes a drift region, a body region between the drift region and the first main surface, an active trench at the first main surface extending into the drift region, a gate insulating layer at sidewalls and a bottom side of the active trench, a gate conductive layer in the active trench, a source region in the body region, and adjacent to the active trench, a body trench at the first main surface extending into the drift region, the body trench being adjacent to the body region and to the drift region, an insulating layer at sidewalls and at a bottom side of the body trench, the insulating layer being asymmetric with respect to an axis extending perpendicular to the first main surface at a center of the body trench, and a conductive layer in the body trench.

公开(公告)号：US20160204097A1

公开(公告)日：2016-07-14

申请号：US14971677

申请日：2015-12-16

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Roman Baburske ,  Thomas Basler ,  Philip Christoph Brandt ,  Maria Cotorogea

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/861 ,  H01L29/423 ,  H01L29/739 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L27/0266 ,  H01L27/0255 ,  H01L27/0262 ,  H01L29/0684 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/7397 ,  H01L29/861 ,  H01L29/8613 ,  H03K17/0828

Abstract: A semiconductor device includes a semiconductor region having charge carriers of a first conductivity type, a transistor cell in the semiconductor region, and a semiconductor channel region in the transistor cell and having a first doping concentration of charge carriers of a second conductivity type. A semiconductor auxiliary region in the semiconductor region has a second doping concentration of charge carriers of the second conductivity type, which is at least 30% higher than the first doping concentration. A pn-junction between the semiconductor auxiliary region and the semiconductor region is positioned as deep or deeper in the semiconductor region as a pn-junction between the semiconductor channel region and the semiconductor region. The semiconductor auxiliary region is positioned closer to the semiconductor channel region than any other semiconductor region having charge carriers of the second conductivity type and that forms a further pn-junction with the semiconductor region.

Abstract translation: 半导体器件包括具有第一导电类型的电荷载流子的半导体区域，半导体区域中的晶体管单元和晶体管单元中的半导体沟道区域，并且具有第二导电类型的电荷载流子的第一掺杂浓度。 半导体区域中的半导体辅助区域具有第二导电类型的电荷载流子的第二掺杂浓度，其比第一掺杂浓度高至少30％。 半导体辅助区域和半导体区域之间的pn结位于作为半导体沟道区域和半导体区域之间的pn结的半导体区域中的深度或深度。 半导体辅助区域比具有第二导电类型的电荷载流子的任何其它半导体区域更靠近半导体沟道区并且与半导体区域形成另外的pn结。

公开(公告)号：US09142655B2

公开(公告)日：2015-09-22

申请号：US13796287

申请日：2013-03-12

Applicant: Infineon Technologies AG

Inventor： Maria Cotorogea ,  Frank Wolter ,  Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Yvonne Gawlina-Schmidl

IPC: H01L29/739 ,  H01L29/40 ,  H01L29/08

CPC classification number: H01L29/7397 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/0623 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/7395 ,  H01L29/7813

Abstract: A semiconductor device in a semiconductor substrate includes a first main surface and a transistor cell. The transistor cell includes a drift region of a first conductivity type, a body region of a second conductivity type between the drift region and the first main surface, an active trench in the first main surface extending to the drift region, a source region of the first conductivity in the body region adjacent to the active trench, and a body trench at the first main surface extending to the drift region and adjacent to the body region and the drift region. The active trench includes a gate insulating layer at sidewalls and a bottom side, and a gate conductive layer. The body trench includes a conductive layer and an insulating layer at sidewalls and a bottom side, and asymmetric to a perpendicular axis of the first main surface and the body trench center.

Abstract translation: 半导体衬底中的半导体器件包括第一主表面和晶体管单元。 晶体管单元包括第一导电类型的漂移区域，漂移区域和第一主表面之间的第二导电类型的体区域，延伸到漂移区域的第一主表面中的有源沟槽，源极区域 在与主动沟槽相邻的主体区域中的第一导电性，以及在第一主表面处延伸到漂移区并且与身体区域和漂移区域相邻的主体沟槽。 有源沟槽包括在侧壁和底侧的栅极绝缘层和栅极导电层。 主体沟槽包括在侧壁和底侧的导电层和绝缘层，并且与第一主表面和体沟槽中心的垂直轴不对称。