公开(公告)号：US09711621B2

公开(公告)日：2017-07-18

申请号：US14446741

申请日：2014-07-30

Applicant: Infineon Technologies AG

Inventor： Franz Hirler ,  Uwe Wahl ,  Thorsten Meyer ,  Michael Rüb ,  Armin Willmeroth ,  Markus Schmitt ,  Carolin Tolksdorf ,  Carsten Schaeffer

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/265 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/66689 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66704 ,  H01L29/78 ,  H01L29/7825

Abstract: A trench transistor having a semiconductor body includes a source region, a body region, a drain region electrically connected to a drain contact, and a gate trench including a gate electrode which is isolated from the semiconductor body. The gate electrode is configured to control current flow between the source region and the drain region along at least a first side wall of the gate trench. The trench transistor further includes a doped semiconductor region having dopants introduced into the semiconductor body through an unmasked part of the walls of a trench.

公开(公告)号：US20130330908A1

公开(公告)日：2013-12-12

申请号：US13966915

申请日：2013-08-14

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Helmut Strack ,  Armin Willmeroth ,  Hans-Joachim Schulze

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/161 ,  H01L29/165 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/7831

Abstract: A semiconductor component with vertical structures having a high aspect ratio and method. In one embodiment, a drift zone is arranged between a first and a second component zone. A drift control zone is arranged adjacent to the drift zone in a first direction. A dielectric layer is arranged between the drift zone and the drift control zone wherein the drift zone has a varying doping and/or a varying material composition at least in sections proceeding from the dielectric.

Abstract translation: 具有高纵横比和垂直结构的半导体元件。 在一个实施例中，漂移区布置在第一和第二组分区之间。 漂移控制区在第一方向上布置成与漂移区相邻。 电介质层布置在漂移区和漂移控制区之间，其中漂移区具有至少在从电介质进行的部分中的变化的掺杂和/或变化的材料组成。

公开(公告)号：US20240194778A1

公开(公告)日：2024-06-13

申请号：US18080427

申请日：2022-12-13

Applicant: Infineon Technologies AG

Inventor： Michael Hell ,  Rudolf Elpelt ,  Frank Hille ,  Caspar Leendertz ,  Armin Willmeroth

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/7811 ,  H01L21/26513 ,  H01L21/266 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1608

Abstract: A semiconductor device includes: a semiconductor substrate having an active device region that includes a plurality of device cells and a termination region between the active device region and an edge of the semiconductor substrate; a field termination structure in the termination region and including a continuous region of a first conductivity type and a plurality of rings of the first conductivity type in the continuous region and having a higher average doping concentration than the continuous region; and a charge balance structure in the active device region and including interleaved columns of the first conductivity type and of a second conductivity type opposite the first conductivity type. The charge balance structure extends into the termination region below the field termination structure such that at least an outermost one of the columns of the first conductivity type is connected to the continuous region of the field termination structure.

公开(公告)号：US20140332885A1

公开(公告)日：2014-11-13

申请号：US14446741

申请日：2014-07-30

Applicant: Infineon Technologies AG

Inventor： Franz Hirler ,  Uwe Wahl ,  Thorsten Meyer ,  Michael Rüb ,  Armin Willmeroth ,  Markus Schmitt ,  Carolin Tolksdorf ,  Carsten Schaeffer

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66689 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66704 ,  H01L29/78 ,  H01L29/7825

Abstract: A lateral trench transistor has a semiconductor body having a source region, a source contact, a body region, a drain region, and a gate trench, in which a gate electrode which is isolated from the semiconductor body is embedded. A heavily doped semiconductor region is provided within the body region or adjacent to it, and is electrically connected to the source contact, and whose dopant type corresponds to that of the body region.

Abstract translation: 横向沟槽晶体管具有半导体本体，其具有嵌入与半导体本体隔离的栅电极的源极区，源极接触，体区，漏极区和栅极沟槽。 重掺杂半导体区域设置在体区内或与其相邻，并且与源极接触电连接，并且其掺杂剂类型对应于身体区域。

公开(公告)号：US08815686B2

公开(公告)日：2014-08-26

申请号：US13803291

申请日：2013-03-14

Applicant: Infineon Technologies AG

Inventor： Franz Hirler ,  Uwe Wahl ,  Thorsten Meyer ,  Michael Rüb ,  Armin Willmeroth ,  Markus Schmitt ,  Carolin Tolksdorf ,  Carsten Schaeffer

IPC: H01L21/336

CPC classification number: H01L29/66689 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66704 ,  H01L29/78 ,  H01L29/7825

Abstract: A method for production of doped semiconductor regions in a semiconductor body of a lateral trench transistor includes forming a trench in the semiconductor body and introducing dopants into at least one area of the semiconductor body that is adjacent to the trench, by carrying out a process in which dopants enter the at least one area through inner walls of the trench.

Abstract translation: 在横向沟槽晶体管的半导体本体中制造掺杂半导体区域的方法包括：在半导体本体中形成沟槽，并且通过在半导体本体中进行工艺，将掺杂物引入与沟槽相邻的半导体本体的至少一个区域中 所述掺杂剂通过沟槽的内壁进入至少一个区域。

公开(公告)号：US20140070323A1

公开(公告)日：2014-03-13

申请号：US13774492

申请日：2013-02-22

Applicant: Infineon Technologies AG

Inventor： Armin Willmeroth ,  Marc Fahlenkamp

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H02M1/36

Abstract: A semiconductor arrangement includes a semiconductor body with a first active region, a second active region and an isolation region arranged between the first and the second active regions. At least one source region and at least one body region of a first transistor are integrated in the first active region. At least one source region and at least one body region of a second transistor are integrated in the second active region. Source and body regions of a third transistor are integrated in the second active region. The second transistor and the third transistor have a common source electrode. The first transistor, the second transistor and the third transistor have a common drain electrode.

Abstract translation: 半导体装置包括具有第一有源区的半导体本体，第二有源区和布置在第一和第二有源区之间的隔离区。 第一晶体管的至少一个源极区域和至少一个体区域集成在第一有源区域中。 第二晶体管的至少一个源极区域和至少一个体区域集成在第二有源区域中。 第三晶体管的源极和体区集成在第二有源区中。 第二晶体管和第三晶体管具有公共源电极。 第一晶体管，第二晶体管和第三晶体管具有公共漏电极。

公开(公告)号：US20180013013A1

公开(公告)日：2018-01-11

申请号：US15642893

申请日：2017-07-06

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Frank Dieter Pfirsch ,  Hans-Joachim Schulze ,  Philipp Seng ,  Armin Willmeroth

IPC: H01L29/861 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L21/225 ,  H01L21/266

CPC classification number: H01L29/8611 ,  H01L21/2253 ,  H01L21/2652 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0688 ,  H01L29/08 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/66128 ,  H01L29/66136

Abstract: A semiconductor device includes an anode doping region of a diode structure arranged in a semiconductor substrate. The anode doping region has a first conductivity type. The semiconductor device further includes a second conductivity type contact doping region having a second conductivity type. The second conductivity type contact doping region is arranged at a surface of the semiconductor substrate and surrounded in the semiconductor substrate by the anode doping region. The anode doping region includes a buried non-depletable portion. At least part of the buried non-depletable portion is located below the second conductivity type contact doping region in the semiconductor substrate.

公开(公告)号：US09385119B2

公开(公告)日：2016-07-05

申请号：US13774492

申请日：2013-02-22

Applicant: Infineon Technologies AG

Inventor： Armin Willmeroth ,  Marc Fahlenkamp

IPC: H01L27/088 ,  H02M1/36

CPC classification number: H01L27/088 ,  H02M1/36

Abstract: A semiconductor arrangement includes a semiconductor body with a first active region, a second active region and an isolation region arranged between the first and the second active regions. At least one source region and at least one body region of a first transistor are integrated in the first active region. At least one source region and at least one body region of a second transistor are integrated in the second active region. Source and body regions of a third transistor are integrated in the second active region. The second transistor and the third transistor have a common source electrode. The first transistor, the second transistor and the third transistor have a common drain electrode.

Abstract translation: 半导体装置包括具有第一有源区的半导体本体，第二有源区和布置在第一和第二有源区之间的隔离区。 第一晶体管的至少一个源极区域和至少一个体区域集成在第一有源区域中。 第二晶体管的至少一个源极区域和至少一个体区域集成在第二有源区域中。 第三晶体管的源极和体区集成在第二有源区中。 第二晶体管和第三晶体管具有公共源电极。 第一晶体管，第二晶体管和第三晶体管具有公共漏电极。

公开(公告)号：US10516065B2

公开(公告)日：2019-12-24

申请号：US15642893

申请日：2017-07-06

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Frank Dieter Pfirsch ,  Hans-Joachim Schulze ,  Philipp Seng ,  Armin Willmeroth

IPC: H01L21/00 ,  H01L29/00 ,  H01L29/861 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/36 ,  H01L21/225 ,  H01L21/266 ,  H01L29/16 ,  H01L29/20 ,  H01L21/265

Abstract: A semiconductor device includes an anode doping region of a diode structure arranged in a semiconductor substrate. The anode doping region has a first conductivity type. The semiconductor device further includes a second conductivity type contact doping region having a second conductivity type. The second conductivity type contact doping region is arranged at a surface of the semiconductor substrate and surrounded in the semiconductor substrate by the anode doping region. The anode doping region includes a buried non-depletable portion. At least part of the buried non-depletable portion is located below the second conductivity type contact doping region in the semiconductor substrate.

公开(公告)号：US20130224921A1

公开(公告)日：2013-08-29

申请号：US13803291

申请日：2013-03-14

Applicant: Infineon Technologies AG

Inventor： Franz Hirler ,  Uwe Wahl ,  Thorsten Meyer ,  Michael Rüb ,  Armin Willmeroth ,  Markus Schmitt ,  Carolin Tolksdorf ,  Carsten Schaeffer

IPC: H01L29/66

CPC classification number: H01L29/66689 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66704 ,  H01L29/78 ,  H01L29/7825

Abstract: A method for production of doped semiconductor regions in a semiconductor body of a lateral trench transistor includes forming a trench in the semiconductor body and introducing dopants into at least one area of the semiconductor body that is adjacent to the trench, by carrying out a process in which dopants enter the at least one area through inner walls of the trench.

Abstract translation: 在横向沟槽晶体管的半导体本体中制造掺杂半导体区域的方法包括：在半导体本体中形成沟槽，并且通过在半导体本体中进行工艺，将掺杂物引入与沟槽相邻的半导体本体的至少一个区域中 所述掺杂剂通过沟槽的内壁进入至少一个区域。