Insulated Gate Bipolar Transistor Device Having a Fin Structure

    公开(公告)号:US20190333991A1

    公开(公告)日:2019-10-31

    申请号:US16506429

    申请日:2019-07-09

    摘要: A transistor device includes a first silicon nanowire array-MOSFET and a second silicon nanowire array-MOSFET integrated with a bulk drift region. The first silicon nanowire array-MOSFET is configured as an n-MOSFET by substantially only accommodating an electron current, and the second silicon nanowire array-MOSFET is configured as a p-MOSFET by substantially only accommodating a hole electron current. A current strength of a current through the first silicon nanowire array-MOSFET caused by electrons is at least 10 times larger than a current through the first silicon nanowire array-MOSFET caused by holes in an on-state of the transistor device. Further embodiments of transistor devices are described.

    Insulated gate bipolar transistor device having a fin structure

    公开(公告)号:US11038016B2

    公开(公告)日:2021-06-15

    申请号:US16929637

    申请日:2020-07-15

    摘要: A transistor device includes a first silicon nanowire array-MOSFET and a second silicon nanowire array-MOSFET integrated with a bulk drift region. The first silicon nanowire array-MOSFET is configured as an n-MOSFET by substantially only accommodating an electron current, and the second silicon nanowire array-MOSFET is configured as a p-MOSFET by substantially only accommodating a hole electron current. A current strength of a current through the first silicon nanowire array-MOSFET caused by electrons is at least 10 times larger than a current through the first silicon nanowire array-MOSFET caused by holes in an on-state of the transistor device. Further embodiments of transistor devices are described.

    Insulated gate bipolar Transistor device having a fin structure

    公开(公告)号:US10748995B2

    公开(公告)日:2020-08-18

    申请号:US16506429

    申请日:2019-07-09

    摘要: A transistor device includes a first silicon nanowire array-MOSFET and a second silicon nanowire array-MOSFET integrated with a bulk drift region. The first silicon nanowire array-MOSFET is configured as an n-MOSFET by substantially only accommodating an electron current, and the second silicon nanowire array-MOSFET is configured as a p-MOSFET by substantially only accommodating a hole electron current. A current strength of a current through the first silicon nanowire array-MOSFET caused by electrons is at least 10 times larger than a current through the first silicon nanowire array-MOSFET caused by holes in an on-state of the transistor device. Further embodiments of transistor devices are described.