公开(公告)号：US20240290828A1

公开(公告)日：2024-08-29

申请号：US18426051

申请日：2024-01-29

申请人： Littelfuse Semiconductor (Wuxi) Co., Ltd.

发明人： Xingchong Gu ,  Jifeng Zhou

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/0619 ,  H01L29/0834 ,  H01L29/1012 ,  H01L29/66363

摘要： Techniques for reducing peak on-state voltage of a semiconductor device fabricated in a wafer. A substrate layer is provided. An isolation structure is provided to laterally isolate the semiconductor device from other semiconductor devices in the wafer. A tub structure is formed in the substrate layer. A base layer is provided such that the base layer is disposed under the substrate layer. The base layer includes an anode having an associated active region that includes a drift region in the substrate layer. The tub structure is disposed inside the active region such that presence of the tub structure reduces a thickness of the drift region.

公开(公告)号：US20230317818A1

公开(公告)日：2023-10-05

申请号：US18023982

申请日：2021-08-19

申请人： Hitachi Energy Switzerland AG

发明人： Jan VOBECKY ,  Umamaheswara VEMULAPATI

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06 ,  H01L29/74

CPC分类号： H01L29/66363 ,  H01L29/0692 ,  H01L29/0839 ,  H01L29/41716 ,  H01L29/42308 ,  H01L29/74

摘要： Disclosed is a power semiconductor device comprising a semiconductor wafer having a first main side and second main side. The semiconductor wafer comprises parallel thyristor cells, which each comprises (a) a cathode electrode and gate electrode on the first main side; (b) a cathode layer comprising a cathode region of a first conductivity type, forming an ohmic contact with the cathode electrode; (c) a first base layer of a second conductivity type, wherein the cathode region forms a p-n junction between the first base layer and cathode region; (d) a second base layer of the first conductivity type forming a second p-n junction with the first base layer; (e) an anode layer of the second conductivity type separated from the first base layer by the second base layer. The gate electrodes of the plurality of thyristor cells form a gate design comprising multiple polygons each comprising at least four struts.

公开(公告)号：US10002954B2

公开(公告)日：2018-06-19

申请号：US15100286

申请日：2014-01-24

申请人： Walid M. Hafez ,  Chia-Hong Jan

发明人： Walid M. Hafez ,  Chia-Hong Jan

IPC分类号： H01L29/66 ,  H01L29/74 ,  H01L29/417 ,  H01L29/06 ,  H01L27/02 ,  H01L21/225 ,  H01L29/78

CPC分类号： H01L29/74 ,  H01L21/2255 ,  H01L27/0262 ,  H01L29/0649 ,  H01L29/41716 ,  H01L29/66363 ,  H01L29/785

摘要： Embodiments of semiconductor devices, integrated circuit devices and methods are disclosed. In some embodiments, a semiconductor device may include a first fin and a second fin disposed on a substrate. The first fin may have a portion including a first material disposed between a second material and the substrate, the second material disposed between a third material and the first material, and the third material disposed between a fourth material and the second material. The first and third materials may be formed from a first type of extrinsic semiconductor, and the second and fourth materials may be formed from a second, different type of extrinsic semiconductor. The second fin may be laterally separated from the first fin and materially contiguous with at least one of the first, second, third or fourth materials. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US20180151367A1

公开(公告)日：2018-05-31

申请号：US15459099

申请日：2017-03-15

申请人： ABB SCHWEIZ AG

发明人： WOLFGANG JANISCH ,  ATZE DE VRIES ,  SVEN MATTHIAS

IPC分类号： H01L21/225 ,  H01L21/673 ,  H01L29/66 ,  H01L21/283

CPC分类号： H01L21/225 ,  H01L21/2007 ,  H01L21/2253 ,  H01L21/2256 ,  H01L21/283 ,  H01L21/673 ,  H01L21/76256 ,  H01L29/0834 ,  H01L29/0873 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/7395 ,  H01L29/744

摘要： A method for manufacturing a vertical power semiconductor device is provided, wherein a first impurity is provided at the first main side of a semiconductor wafer. A first oxide layer is formed on the first main side of the wafer, wherein the first oxide layer is partially doped with a second impurity in such way that any first portion of the first oxide layer which is doped with the second impurity is spaced away from the semiconductor wafer by a second portion of the first oxide layer which is not doped with the second impurity and which is disposed between the first portion of the first oxide layer and the first main side of the semiconductor wafer. Thereafter a carrier wafer is bonded to the first oxide layer. During front-end-of-line processing on the second main side of the semiconductor wafer, the second impurity is diffused from the first oxide layer into the semiconductor wafer from its first main side by heat generated during the front-end-of-line processing.

公开(公告)号：US09728634B2

公开(公告)日：2017-08-08

申请号：US15003246

申请日：2016-01-21

申请人： Micron Technology, Inc.

发明人： Marcello Mariani ,  Carlo Pozzi

IPC分类号： H01L29/74 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L27/108 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/24 ,  H01L29/788 ,  H01L29/792 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L29/7827 ,  H01L21/2815 ,  H01L27/10805 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/2454 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66363 ,  H01L29/66666 ,  H01L29/74 ,  H01L29/7889 ,  H01L29/7926

摘要： Methods of fabricating vertical devices are described, along with apparatuses and systems that include them. In one such method, a vertical device is formed at least partially in a void in a first dielectric material and a second dielectric material. Additional embodiments are also described.

公开(公告)号：US09620630B2

公开(公告)日：2017-04-11

申请号：US15072218

申请日：2016-03-16

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Madhur Bobde ,  Jun Hu ,  Lingpeng Guan ,  Hamza Yilmaz ,  Lei Zhang ,  Jongoh Kim

IPC分类号： H01L29/739 ,  H01L29/36 ,  H01L29/10 ,  H01L29/06 ,  H01L29/74 ,  H01L29/66 ,  H01L21/265 ,  H01L21/20 ,  H01L29/08 ,  H01L21/266 ,  H01L29/423

CPC分类号： H01L29/7395 ,  H01L21/20 ,  H01L21/26513 ,  H01L21/266 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/107 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66363 ,  H01L29/7397 ,  H01L29/74

摘要： Semiconductor power devices can be formed on substrate structure having a lightly doped semiconductor substrate of a first conductivity type or a second conductivity type opposite to the first conductivity type. A semiconductive first buffer layer of the first conductivity type formed above the substrate. A doping concentration of the first buffer layer is greater than a doping concentration of the substrate. A second buffer layer of the second conductivity type formed above the first buffer layer. An epitaxial layer of the second conductivity type formed above the second buffer layer. One or more heavily doped regions of the second conductivity type are formed through portions of the first buffer layer from the second buffer layer and into corresponding portions of the substrate. This abstract is provided with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

公开(公告)号：US20170033208A1

公开(公告)日：2017-02-02

申请号：US15290377

申请日：2016-10-11

申请人： ABB Schweiz AG

发明人： Hendrik Ravener ,  Tobias Wikström ,  Hermann Amstutz ,  Norbert Meier

IPC分类号： H01L29/745 ,  H01L23/31 ,  H01L21/56 ,  H01L29/45 ,  H01L29/66 ,  H01L23/051 ,  H01L29/74

CPC分类号： H01L29/745 ,  H01L21/565 ,  H01L23/051 ,  H01L23/3185 ,  H01L29/45 ,  H01L29/66363 ,  H01L29/7416 ,  H01L29/7424 ,  H01L29/744 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present application relates to a turn-off power semiconductor device having a wafer with an active region and a termination region surrounding the active region, a rubber ring as an edge passivation for the wafer and a gate ring placed on a ring-shaped gate contact on the termination region for contacting the gate electrodes of a thyristor cell formed in the active region of the wafer. In the turn-off power semiconductor device, the outer circumferential surface of the gate ring is in contact with the rubber ring to define the inner border of the rubber ring. The area consumed by the ring-shaped gate contact on the termination or edge region can be minimized. The upper surface of the gate ring and the upper surface of the rubber ring form a continuous surface extending in a plane parallel to the first main side of the wafer.

摘要翻译： 本发明涉及具有有源区和围绕有源区的端接区的晶片的截止功率半导体器件，作为晶片的边缘钝化的橡胶环和放置在环形栅极接触上的栅极环 在用于接触形成在晶片的有源区域中的晶闸管电池的栅电极的端接区域上。 在关断功率半导体器件中，门环的外周面与橡胶环接触以限定橡胶环的内边界。 可以使终端或边缘区域上的环状栅极接触消耗的面积最小化。 门环的上表面和橡胶环的上表面形成在与晶片的第一主侧平行的平面中延伸的连续表面。

公开(公告)号：US20170025163A1

公开(公告)日：2017-01-26

申请号：US15283141

申请日：2016-09-30

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng

IPC分类号： G11C11/39 ,  G11C11/4096 ,  H01L27/102 ,  H01L29/74 ,  H01L21/265 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  G11C11/406 ,  H01L29/66

CPC分类号： G11C11/39 ,  G11C11/401 ,  G11C11/402 ,  G11C11/406 ,  G11C11/4096 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/76224 ,  H01L27/1027 ,  H01L29/0649 ,  H01L29/66363 ,  H01L29/74

摘要： A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read, write, retain and refresh data stored therein.

摘要翻译： 公开了使用垂直晶闸管的易失性存储器阵列以及操作阵列以读取，写入，保留和刷新存储在其中的数据的方法。

公开(公告)号：US09520285B2

公开(公告)日：2016-12-13

申请号：US14350916

申请日：2012-10-23

申请人： Anvil Semiconductors Limited

发明人： Peter Ward

IPC分类号： H01L29/15 ,  H01L21/02 ,  H01L29/66 ,  H01L29/739 ,  H01L29/04 ,  H01L29/16 ,  H01L29/74 ,  H01L21/308

CPC分类号： H01L21/02529 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0262 ,  H01L21/02642 ,  H01L21/02645 ,  H01L21/3081 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66363 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/74

摘要： A method comprises providing a monocrystalline silicon wafer (11) having a principal surface (17) which supports a masking layer (24), for example silicon dioxide or polycrystalline silicon, having windows (25) to expose corresponding regions of the silicon wafer, forming silicon carbide seed regions (30) on the exposed regions of the wafer, for example by forming carbon and converting the carbon into silicon carbide, and growing monocrystalline silicon carbide (31) on the silicon carbide seed regions. Thus, monocrystalline silicon carbide can be formed selectively on the silicon wafer which can help to avoid wafer bow.

摘要翻译： 一种方法包括提供具有主表面（17）的单晶硅晶片（11），其支撑掩模层（24），例如二氧化硅或多晶硅，具有窗口（25）以暴露硅晶片的相应区域，形成 碳化硅种子区域（30），例如通过形成碳并将碳转化为碳化硅，以及在碳化硅种子区域上生长单晶碳化硅（31）。 因此，可以在硅晶片上选择性地形成单晶碳化硅，这有助于避免晶片弓形。

公开(公告)号：US09496148B1

公开(公告)日：2016-11-15

申请号：US14850491

申请日：2015-09-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Sunit S. Mahajan ,  Bachir Dirahoui ,  Richard Wise

IPC分类号： H01L21/3065 ,  H01L21/768 ,  H01L21/683 ,  H01L29/06 ,  H01L21/31 ,  H01L21/223

CPC分类号： H01L21/3065 ,  H01J37/32009 ,  H01J37/32532 ,  H01J2237/334 ,  H01L21/6833 ,  H01L21/76898 ,  H01L29/66363

摘要： A method of reactive ion etching a wafer includes providing a plasma processing tool having a wafer chuck within a chamber and an electrode creating a plasma above the wafer chuck. There is provided on the wafer chuck a semiconductor wafer having a p− layer and an n+ layer. Both p− and n+ layers have exposed peripheral edges during plasma etching to electrically form with the plasma processing tool during plasma etching a diode having an anode comprising the plasma, a cathode comprising the wafer chuck and a gate comprising the n+ layer peripheral edge. The method includes controlling charge flow during plasma etching adjacent the peripheral edge of the n+ layer to reduce charge transport into, within and out of the semiconductor wafer adjacent the n+ layer edge, and reactive ion etching the n+ layer while controlling the charge flow along the edge of the n+ layer.

摘要翻译： 一种反应离子蚀刻晶片的方法包括提供等离子体处理工具，该等离子体处理工具在腔室内具有晶片卡盘，并且在晶片卡盘上形成等离子体的电极。 在晶片卡盘上设置有具有p层和n +层的半导体晶片。 在等离子体蚀刻期间，等离子体蚀刻期间，p型和n +层都具有暴露的外围边缘，以在等离子体蚀刻期间具有包括等离子体的阳极的二极管，包括晶片卡盘的阴极和包括n +层周边的栅极。 该方法包括控制邻近n +层的周边边缘的等离子体蚀刻期间的电荷流动，以减少进入与n +层边缘相邻的半导体晶片的内部和外部的电荷传输，以及反应离子蚀刻n +层，同时控制沿着n + n +层的边缘。