公开(公告)号：US08669651B2

公开(公告)日：2014-03-11

申请号：US12843549

申请日：2010-07-26

Applicant: Chung-Ying Yang ,  Chao-Wen Shih ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Mirng-Ji Lii ,  Tzuan-Horng Liu

Inventor： Chung-Ying Yang ,  Chao-Wen Shih ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Mirng-Ji Lii ,  Tzuan-Horng Liu

IPC: H01L23/538

CPC classification number: H01L23/5385 ,  H01L23/3121 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A device includes a package substrate including a first non-reflowable metal bump extending over a top surface of the package substrate; a die over and bonded to the package substrate; and a package component over the die and bonded to the package substrate. The package component includes a second non-reflowable metal bump extending below a bottom surface of the package component. The package component is selected from the group consisting essentially of a device die, an additional package substrate, and combinations thereof. A solder bump bonds the first non-reflowable metal bump to the second non-reflowable metal bump.

Abstract translation: 一种器件包括封装衬底，其包括在封装衬底的顶表面上延伸的第一不可回流金属凸块; 并且结合到封装基板上; 以及在所述管芯上并且结合到所述封装衬底的封装部件。 包装部件包括在包装部件的底部表面下方延伸的第二不可回流金属凸块。 封装部件选自基本上由器件管芯，附加封装衬底及其组合组成的组。 焊料凸块将第一不可回流金属凸块接合到第二不可回流金属凸块。

公开(公告)号：US08558229B2

公开(公告)日：2013-10-15

申请号：US13313747

申请日：2011-12-07

Applicant: Shin-Puu Jeng ,  Wei-Cheng Wu ,  Shang-Yun Hou ,  Chen-Hua Yu ,  Tzuan-Horng Liu ,  Tzu-Wei Chiu ,  Kuo-Ching Hsu

Inventor： Shin-Puu Jeng ,  Wei-Cheng Wu ,  Shang-Yun Hou ,  Chen-Hua Yu ,  Tzuan-Horng Liu ,  Tzu-Wei Chiu ,  Kuo-Ching Hsu

IPC: H01L23/58

CPC classification number: H01L22/34 ,  G01R31/2884 ,  H01L21/76885 ,  H01L22/32 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02126 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/10126 ,  H01L2224/13005 ,  H01L2224/16225 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/00

Abstract: The embodiments described above provide mechanisms for forming metal bumps on metal pads with testing pads on a packaged integrated circuit (IC) chip. A passivation layer is formed to cover the testing pads and possibly portions of metal pads. The passivation layer does not cover surfaces away from the testing pad region and the metal pad region. The limited covering of the testing pads and the portions of the metal pads by the passivation layer reduces interface resistance for a UBM layer formed between the metal pads and the metal bumps. Such reduction of interface resistance leads to the reduction of resistance of the metal bumps.

Abstract translation: 上述实施例提供了在封装的集成电路（IC）芯片上用测试焊盘在金属焊盘上形成金属凸块的机构。 形成钝化层以覆盖测试焊盘和可能的金属焊盘部分。 钝化层不覆盖远离测试焊盘区域和金属焊盘区域的表面。 通过钝化层测试焊盘和金属焊盘部分的有限覆盖减少了形成在金属焊盘和金属凸块之间的UBM层的界面电阻。 这种界面电阻的降低导致金属凸块的电阻降低。

公开(公告)号：US08753971B2

公开(公告)日：2014-06-17

申请号：US13427430

申请日：2012-03-22

Applicant: Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

Inventor： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

IPC: H01L21/44

CPC classification number: H01L23/585 ,  H01L23/552 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/13655 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method of forming an integrated circuit structure is provided. The method includes forming a metal pad at a major surface of a semiconductor chip, forming an under-bump metallurgy (UBM) over the metal pad such that the UBM and the metal pad are in contact, forming a dummy pattern at a same level as the metal pad, the dummy pattern formed of a same metallic material as the metal pad and electrically disconnected from the metal pad, and forming a metal bump over the UBM such that the metal bump is electrically connected to the UBM and no metal bump in the semiconductor chip is formed over the dummy pattern.

Abstract translation: 提供一种形成集成电路结构的方法。 该方法包括在半导体芯片的主表面上形成金属焊盘，在金属焊盘上形成凸块下冶金（UBM），使得UBM和金属焊盘接触，形成与 金属焊盘，由与金属焊盘相同的金属材料形成的虚拟图案，并与金属焊盘电气断开，并在UBM上形成金属凸块，使得金属凸块电连接到UBM，并且在金属焊盘中没有金属凸块 在虚拟图案上形成半导体芯片。

公开(公告)号：US08610267B2

公开(公告)日：2013-12-17

申请号：US12840900

申请日：2010-07-21

Applicant: Ching-Jung Yang ,  Chang-Pin Huang ,  Tzuan-Horng Liu ,  Michael Shou-Ming Tong ,  Ying-Ju Chen ,  Tung-Liang Shao ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii

Inventor： Ching-Jung Yang ,  Chang-Pin Huang ,  Tzuan-Horng Liu ,  Michael Shou-Ming Tong ,  Ying-Ju Chen ,  Tung-Liang Shao ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii

IPC: H01L23/48

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/93 ,  H01L25/0657 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81464 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A die includes a metal pad, a passivation layer, and a patterned buffer layer over the passivation layer. The patterned buffer layer includes a plurality of discrete portions separated from each other. An under-bump-metallurgy (UBM) is formed in an opening in the patterned buffer layer and an opening in the passivation layer. A metal bump is formed over and electrically coupled to the UBM.

公开(公告)号：US20120178252A1

公开(公告)日：2012-07-12

申请号：US13427430

申请日：2012-03-22

Applicant: Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

Inventor： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

IPC: H01L21/768

CPC classification number: H01L23/585 ,  H01L23/552 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/13655 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method of forming an integrated circuit structure is provided. The method includes forming a metal pad at a major surface of a semiconductor chip, forming an under-bump metallurgy (UBM) over the metal pad such that the UBM and the metal pad are in contact, forming a dummy pattern at a same level as the metal pad, the dummy pattern formed of a same metallic material as the metal pad and electrically disconnected from the metal pad, and forming a metal bump over the UBM such that the metal bump is electrically connected to the UBM and no metal bump in the semiconductor chip is formed over the dummy pattern.

Abstract translation: 提供一种形成集成电路结构的方法。 该方法包括在半导体芯片的主表面上形成金属焊盘，在金属焊盘上形成凸块下冶金（UBM），使得UBM和金属焊盘接触，形成与 金属焊盘，由与金属焊盘相同的金属材料形成的虚拟图案，并与金属焊盘电气断开，并在UBM上形成金属凸块，使得金属凸块电连接到UBM，并且在金属焊盘中没有金属凸块 在虚拟图案上形成半导体芯片。

公开(公告)号：US20110018128A1

公开(公告)日：2011-01-27

申请号：US12757440

申请日：2010-04-09

Applicant: Hsiu-Ping WEI ,  Shin-Puu JENG ,  Hao-Yi TSAI ,  Hsien-Wei CHEN ,  Yu-Wen LIU ,  Ying-Ju CHEN ,  Tzuan-Horng LIU

Inventor： Hsiu-Ping WEI ,  Shin-Puu JENG ,  Hao-Yi TSAI ,  Hsien-Wei CHEN ,  Yu-Wen LIU ,  Ying-Ju CHEN ,  Tzuan-Horng LIU

IPC: H01L23/498 ,  H01L21/3205

CPC classification number: H01L21/76801 ,  H01L23/3192 ,  H01L23/522 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor package structure is provided. The structure includes a semiconductor chip having a plurality of interconnect layers formed thereover. A first passivation layer is formed over the plurality of interconnect layers. A stress buffer layer is formed over the first passivation layer. A bonding pad is formed over the stress buffer layer. A second passivation layer is formed over a portion of the bonding pad, the second passivation having at least one opening therein exposing a portion of the bonding pad.

Abstract translation: 提供半导体封装结构。 该结构包括其上形成有多个互连层的半导体芯片。 在多个互连层上形成第一钝化层。 在第一钝化层上形成应力缓冲层。 在应力缓冲层上形成接合焊盘。 在接合焊盘的一部分上形成第二钝化层，第二钝化层具有至少一个开口，露出焊接区的一部分。

公开(公告)号：US08659170B2

公开(公告)日：2014-02-25

申请号：US12905276

申请日：2010-10-15

Applicant: Chen-Cheng Kuo ,  Tzuan-Horng Liu ,  Chen-Shien Chen

Inventor： Chen-Cheng Kuo ,  Tzuan-Horng Liu ,  Chen-Shien Chen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44

CPC classification number: H01L24/06 ,  H01L21/76838 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/0501 ,  H01L2224/0502 ,  H01L2224/05085 ,  H01L2224/05099 ,  H01L2224/0556 ,  H01L2224/05599 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2224/13099 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor device includes at least two conductive pads, one of the conductive pads being formed above another of the at least two conductive pads, and a redistribution layer extending from at least one of the conductive pads. The semiconductor device also includes a bump structure formed over the conductive pads and electrically coupled to the conductive pads.

Abstract translation: 半导体器件包括至少两个导电焊盘，其中一个导电焊盘形成在至少两个导电焊盘的另一个之上，以及从至少一个导电焊盘延伸的再分配层。 半导体器件还包括形成在导电焊盘上并且电耦合到导电焊盘的凸块结构。

公开(公告)号：US20130147032A1

公开(公告)日：2013-06-13

申请号：US13313747

申请日：2011-12-07

Applicant: Shin-Puu JENG ,  Wei-Cheng WU ,  Shang-Yun HOU ,  Chen-Hua YU ,  Tzuan-Horng LIU ,  Tzu-Wei CHIU ,  Kuo-Ching HSU

Inventor： Shin-Puu JENG ,  Wei-Cheng WU ,  Shang-Yun HOU ,  Chen-Hua YU ,  Tzuan-Horng LIU ,  Tzu-Wei CHIU ,  Kuo-Ching HSU

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L22/34 ,  G01R31/2884 ,  H01L21/76885 ,  H01L22/32 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02126 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/10126 ,  H01L2224/13005 ,  H01L2224/16225 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/00

Abstract: The embodiments described above provide mechanisms for forming metal bumps on metal pads with testing pads on a packaged integrated circuit (IC) chip. A passivation layer is formed to cover the testing pads and possibly portions of metal pads. The passivation layer does not cover surfaces away from the testing pad region and the metal pad region. The limited covering of the testing pads and the portions of the metal pads by the passivation layer reduces interface resistance for a UBM layer formed between the metal pads and the metal bumps. Such reduction of interface resistance leads to the reduction of resistance of the metal bumps.

Abstract translation: 上述实施例提供了在封装的集成电路（IC）芯片上用测试焊盘在金属焊盘上形成金属凸块的机构。 形成钝化层以覆盖测试焊盘和可能的金属焊盘部分。 钝化层不覆盖远离测试焊盘区域和金属焊盘区域的表面。 通过钝化层测试焊盘和金属焊盘部分的有限覆盖减少了形成在金属焊盘和金属凸块之间的UBM层的界面电阻。 这种界面电阻的降低导致金属凸块的电阻降低。

公开(公告)号：US08283781B2

公开(公告)日：2012-10-09

申请号：US12879512

申请日：2010-09-10

Applicant: Wei-Cheng Wu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Tzuan-Horng Liu ,  Tzu-Wei Chiu ,  Chao-Wen Shih

Inventor： Wei-Cheng Wu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Tzuan-Horng Liu ,  Tzu-Wei Chiu ,  Chao-Wen Shih

IPC: H01L29/40

CPC classification number: H01L24/11 ,  H01L23/3114 ,  H01L23/3157 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/0235 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05012 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05541 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/06131 ,  H01L2224/10126 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/35 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01028 ,  H01L2924/01022 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Abstract translation: 半导体器件具有在金属焊盘和凸块下金属化（UBM）层之间具有环形应力缓冲层的焊盘结构。 应力缓冲层由介电常数小于3.5的介质层，聚合物层或铝层形成。 应力缓冲层是圆形环，方形环，八角形环或任何其它几何环。

公开(公告)号：US08193639B2

公开(公告)日：2012-06-05

申请号：US12750468

申请日：2010-03-30

Applicant: Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

Inventor： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

IPC: H01L23/485

CPC classification number: H01L23/585 ,  H01L23/552 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/13655 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An integrated circuit structure includes a semiconductor chip, a metal pad at a major surface of the semiconductor chip, and an under-bump metallurgy (UBM) over and contacting the metal pad. A metal bump is formed over and electrically connected to the UBM. A dummy pattern is formed at a same level, and formed of a same metallic material, as the metal pad.

Abstract translation: 集成电路结构包括半导体芯片，在半导体芯片的主表面处的金属焊盘和在凸块下金属（UBM）上并与金属焊盘接触的集成电路结构。 金属凸块形成在UBM上并与UBM电连接。 在同一水平上形成虚拟图案，并由与金属垫相同的金属材料形成。