公开(公告)号：US09337123B2

公开(公告)日：2016-05-10

申请号：US13546218

申请日：2012-07-11

Applicant: Cheng-Chieh Hsieh ,  Way Lee Cheng ,  Shang-Yun Hou ,  Shin-Puu Jeng

Inventor： Cheng-Chieh Hsieh ,  Way Lee Cheng ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC: H01L23/367 ,  H01L23/427 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/427 ,  H01L21/563 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/562 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/06589

Abstract: One or more heat pipes are utilized along with a substrate in order to provide heat dissipation through the substrate for heat that can build up at an interface between the substrate and one or more semiconductor chips in a package. In an embodiment the heat pipe may be positioned on a side of the substrate opposite the semiconductor chip and through-substrate vias may be utilized to dissipate heat through the substrate. In an alternative embodiment, the heat pipe may be positioned on a same side of the substrate as the semiconductor chip and may be thermally connected to the one or more semiconductor chips.

Abstract translation: 一个或多个热管与衬底一起使用，以便提供通过衬底的热量，其可以在衬底和封装中的一个或多个半导体芯片之间的界面处积聚。 在一个实施例中，热管可以位于与半导体芯片相对的一侧的衬底上，并且通孔衬底可以用于通过衬底散热。 在替代实施例中，热管可以位于与半导体芯片相同的衬底侧上，并且可以热连接到一个或多个半导体芯片。

公开(公告)号：US20140042612A1

公开(公告)日：2014-02-13

申请号：US13569017

申请日：2012-08-07

Applicant: Christianto Chih-Ching Liu ,  Shuo-Mao Chen ,  Der-Chyang Yeh ,  Shang-Yun Hou ,  Shin-Puu Jeng

Inventor： Christianto Chih-Ching Liu ,  Shuo-Mao Chen ,  Der-Chyang Yeh ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L21/02

CPC classification number: H01L23/5226 ,  H01L21/76807 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2924/0002 ,  H05K1/0215 ,  H01L2924/00

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In an embodiment, a method of manufacturing a semiconductor device includes forming a first conductive structure over a workpiece in a first metallization layer, the first conductive structure including a first portion having a first width and a second portion having a second width. The second width is different than the first width. The method includes forming a second conductive structure in a second metallization layer proximate the first metallization layer, and coupling a portion of the second conductive structure to the first portion of the first conductive structure.

Abstract translation: 公开了半导体器件及其制造方法。 在一个实施例中，制造半导体器件的方法包括在第一金属化层中在工件上形成第一导电结构，第一导电结构包括具有第一宽度的第一部分和具有第二宽度的第二部分。 第二宽度与第一宽度不同。 该方法包括在靠近第一金属化层的第二金属化层中形成第二导电结构，以及将第二导电结构的一部分耦合到第一导电结构的第一部分。

公开(公告)号：US08643147B2

公开(公告)日：2014-02-04

申请号：US11933931

申请日：2007-11-01

Applicant: Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Chen-Hua Yu

Inventor： Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Chen-Hua Yu

IPC: H01L23/544

CPC classification number: H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure includes a lower dielectric layer; an upper dielectric layer over the lower dielectric layer; and a seal ring. The seal ring includes an upper metal line in the upper dielectric layer; a continuous via bar underlying and abutting the upper metal line, wherein the continuous via bar has a width greater than about 70 percent of a width of the upper metal line; a lower metal line in the lower dielectric layer; and a via bar underlying and abutting the lower metal line. The via bar has a width substantially less than a half of a width of the lower metal line.

Abstract translation: 集成电路结构包括下介电层; 在下介电层上的上电介质层; 和密封环。 密封环包括在上介电层中的上金属线; 连续的通孔条，其下面并邻接上部金属线，其中所述连续通孔条具有大于所述上部金属线宽度的约70％的宽度; 下介电层中的下金属线; 以及位于下金属线下方并邻接的通孔条。 通孔棒具有基本上小于下金属线宽度的一半的宽度。

公开(公告)号：US08575717B2

公开(公告)日：2013-11-05

申请号：US13090606

申请日：2011-04-20

Applicant: Der-Chyang Yeh ,  Shang-Yun Hou

Inventor： Der-Chyang Yeh ,  Shang-Yun Hou

IPC: H01L29/86

CPC classification number: H01L23/5223 ,  H01L23/5227 ,  H01L27/08 ,  H01L28/10 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a integrated circuit device and a method for fabricating the same. The integrated circuit device includes a semiconductor substrate having a dielectric layer disposed over the semiconductor substrate and a passive element disposed over the dielectric layer. The integrated circuit further includes an isolation matrix structure, underlying the passive element, wherein the isolation matrix structure includes a plurality of trench regions each being formed through the dielectric layer and extending into the semiconductor substrate, the plurality of trench regions further including an insulating material and a void area.

Abstract translation: 提供一种集成电路器件及其制造方法。 集成电路器件包括具有设置在半导体衬底上的电介质层和设置在电介质层上的无源元件的半导体衬底。 所述集成电路还包括在所述无源元件下面的隔离矩阵结构，其中所述隔离矩阵结构包括多个沟槽区，每个沟槽区通过所述电介质层形成并延伸到所述半导体衬底中，所述多个沟槽区还包括绝缘材料 和空隙区域。

公开(公告)号：US08558229B2

公开(公告)日：2013-10-15

申请号：US13313747

申请日：2011-12-07

Applicant: Shin-Puu Jeng ,  Wei-Cheng Wu ,  Shang-Yun Hou ,  Chen-Hua Yu ,  Tzuan-Horng Liu ,  Tzu-Wei Chiu ,  Kuo-Ching Hsu

Inventor： Shin-Puu Jeng ,  Wei-Cheng Wu ,  Shang-Yun Hou ,  Chen-Hua Yu ,  Tzuan-Horng Liu ,  Tzu-Wei Chiu ,  Kuo-Ching Hsu

IPC: H01L23/58

CPC classification number: H01L22/34 ,  G01R31/2884 ,  H01L21/76885 ,  H01L22/32 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02126 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/10126 ,  H01L2224/13005 ,  H01L2224/16225 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/00

Abstract: The embodiments described above provide mechanisms for forming metal bumps on metal pads with testing pads on a packaged integrated circuit (IC) chip. A passivation layer is formed to cover the testing pads and possibly portions of metal pads. The passivation layer does not cover surfaces away from the testing pad region and the metal pad region. The limited covering of the testing pads and the portions of the metal pads by the passivation layer reduces interface resistance for a UBM layer formed between the metal pads and the metal bumps. Such reduction of interface resistance leads to the reduction of resistance of the metal bumps.

Abstract translation: 上述实施例提供了在封装的集成电路（IC）芯片上用测试焊盘在金属焊盘上形成金属凸块的机构。 形成钝化层以覆盖测试焊盘和可能的金属焊盘部分。 钝化层不覆盖远离测试焊盘区域和金属焊盘区域的表面。 通过钝化层测试焊盘和金属焊盘部分的有限覆盖减少了形成在金属焊盘和金属凸块之间的UBM层的界面电阻。 这种界面电阻的降低导致金属凸块的电阻降低。

公开(公告)号：US20130113070A1

公开(公告)日：2013-05-09

申请号：US13292792

申请日：2011-11-09

Applicant: Tzu-Wei Chiu ,  Tzu-Yu Wang ,  Wei-Cheng Wu ,  Chun-Yi Liu ,  Hsien-Pin Hu ,  Shang-Yun Hou

Inventor： Tzu-Wei Chiu ,  Tzu-Yu Wang ,  Wei-Cheng Wu ,  Chun-Yi Liu ,  Hsien-Pin Hu ,  Shang-Yun Hou

IPC: H01L23/525 ,  H01L21/82

CPC classification number: H01L23/49827 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/525 ,  H01L23/5256 ,  H01L23/5382 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/13184 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/00 ,  H01L2224/81805

Abstract: Interposers for semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, an interposer includes a substrate, a contact pad disposed on the substrate, and a first through-via in the substrate coupled to the contact pad. A first fuse is coupled to the first through-via. A second through-via in the substrate is coupled to the contact pad, and a second fuse is coupled to the second through-via.

Abstract translation: 公开了半导体器件用插入件及其制造方法。 在一个实施例中，插入器包括衬底，设置在衬底上的接触焊盘以及耦合到接触焊盘的衬底中的第一通孔。 第一保险丝耦合到第一通孔。 衬底中的第二通孔耦合到接触焊盘，并且第二保险丝耦合到第二通孔。

公开(公告)号：US08334582B2

公开(公告)日：2012-12-18

申请号：US12347026

申请日：2008-12-31

Applicant: Shin-Puu Jeng ,  Hsien-Wei Chen ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Anbiarshy N. F. Wu ,  Yu-Wen Liu

Inventor： Shin-Puu Jeng ,  Hsien-Wei Chen ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Anbiarshy N. F. Wu ,  Yu-Wen Liu

IPC: H01L23/544

CPC classification number: H01L21/78 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor chip includes a semiconductor substrate; a plurality of low-k dielectric layers over the semiconductor substrate; a first passivation layer over the plurality of low-k dielectric layers; and a second passivation layer over the first passivation layer. A first seal ring is adjacent to an edge of the semiconductor chip, wherein the first seal ring has an upper surface substantially level to a bottom surface of the first passivation layer. A second seal ring is adjacent to the first seal ring and on an inner side of the semiconductor chip than the first seal ring. The second seal ring includes a pad ring in the first passivation layer and the second passivation layer. A trench ring includes at least a portion directly over the first seal ring. The trench ring extends from a top surface of the second passivation layer down to at least an interface between the first passivation layer and the second passivation layer.

Abstract translation: 半导体芯片包括半导体衬底; 半导体衬底上的多个低k电介质层; 在所述多个低k电介质层上的第一钝化层; 以及在所述第一钝化层上的第二钝化层。 第一密封环邻近半导体芯片的边缘，其中第一密封环具有基本上平坦于第一钝化层的底表面的上表面。 第二密封环与第一密封环相邻，并且在半导体芯片的内侧与第一密封环相邻。 第二密封环包括在第一钝化层和第二钝化层中的焊盘环。 沟槽环包括直接在第一密封环上的至少一部分。 沟槽环从第二钝化层的顶表面延伸到至少第一钝化层和第二钝化层之间的界面。

公开(公告)号：US20120306073A1

公开(公告)日：2012-12-06

申请号：US13343582

申请日：2012-01-04

Applicant: Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Cheng-Chieh Hsieh ,  Kuo-Ching Hsu ,  Ying-Ching Shih ,  Po-Hoa Tsai ,  Chin-Fu Kao ,  Cheng-Lin Huang ,  Jing-Cheng Lin

Inventor： Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Cheng-Chieh Hsieh ,  Kuo-Ching Hsu ,  Ying-Ching Shih ,  Po-Hoa Tsai ,  Chin-Fu Kao ,  Cheng-Lin Huang ,  Jing-Cheng Lin

IPC: H01L23/485 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/04 ,  H01L25/50 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/10145 ,  H01L2224/10156 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/13578 ,  H01L2224/13686 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/3651 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/049 ,  H01L2924/053 ,  H01L2924/00

Abstract: A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.

Abstract translation: 一种器件包括具有顶表面的顶部电介质层。 金属柱在顶部介电层的顶表面上具有一部分。 在金属柱的侧壁上形成非润湿层，其中非润湿层不能熔化到熔融焊料上。 焊接区域设置在金属柱上并电耦合到金属柱。

公开(公告)号：US20120206160A1

公开(公告)日：2012-08-16

申请号：US13025931

申请日：2011-02-11

Applicant: Wei-Cheng WU ,  Hsien-Pin HU ,  Shang-Yun HOU ,  Shin-Puu JENG ,  Chen-Hua YU ,  Chao-Hsiang YANG

Inventor： Wei-Cheng WU ,  Hsien-Pin HU ,  Shang-Yun HOU ,  Shin-Puu JENG ,  Chen-Hua YU ,  Chao-Hsiang YANG

IPC: G01R31/00

CPC classification number: G01R31/2896 ,  G01R1/0416 ,  G01R31/2601 ,  G01R31/2884 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02377 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/0614 ,  H01L2224/0616 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16238 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014

Abstract: Test structures for performing electrical tests of devices under one or more microbumps are provided. Each test structure includes at least one microbump pad and a test pad. The microbump pad is a part of a metal pad connected to an interconnect for a device. A width of the microbump pad is equal to or less than about 50 μm. The test pad is connected to the at least one microbump pad. The test pad has a size large enough to allow circuit probing of the device. The test pad is another part of the metal pad. A width of the test pad is greater than the at least one microbump pad.

Abstract translation: 提供用于对一个或多个微丸下的装置进行电测试的测试结构。 每个测试结构包括至少一个微型块和测试垫。 微型焊盘是与设备的互连件连接的金属焊盘的一部分。 微型焊盘的宽度等于或小于约50μm。 测试垫连接到至少一个微型块。 测试垫的尺寸足够大以允许设备的电路探测。 测试垫是金属垫的另一部分。 测试垫的宽度大于至少一个微小块垫。

公开(公告)号：US20120049322A1

公开(公告)日：2012-03-01

申请号：US12873931

申请日：2010-09-01

Applicant: An-Jhih Su ,  Chi-Chun Hsieh ,  Tzu-Yu Wang ,  Wei-Cheng Wu ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Wei-Chih Chiou ,  Shin-Puu Jeng

Inventor： An-Jhih Su ,  Chi-Chun Hsieh ,  Tzu-Yu Wang ,  Wei-Cheng Wu ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Wei-Chih Chiou ,  Shin-Puu Jeng

IPC: H01L29/92 ,  H01L21/768

CPC classification number: H01L28/40 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L28/92 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate.

Abstract translation: 一种装置包括具有与前表面相对的前表面和后表面的基底。 电容器形成在衬底中，并包括第一电容器板; 围绕所述第一电容器板的第一绝缘层; 以及环绕所述第一绝缘层的第二电容器板。 第一电容器板，第一绝缘层和第二电容器板中的每一个从衬底的前表面延伸到后表面。