公开(公告)号：US09960088B2

公开(公告)日：2018-05-01

申请号：US13290879

申请日：2011-11-07

申请人： Yi-Chao Mao ,  Jui-Pin Hung ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Yi-Chao Mao ,  Jui-Pin Hung ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： B24B49/10 ,  H01L21/66 ,  B24B37/013 ,  B24B7/22 ,  H01L23/31

CPC分类号： H01L22/26 ,  B24B7/228 ,  B24B37/013 ,  B24B49/10 ,  H01L22/12 ,  H01L23/3114 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for performing grinding includes selecting a target wheel loading for wafer grinding processes, and performing a grinding process on a wafer. With the proceeding of the grinding process, wheel loadings of the grinding process are measured. The grinding process is stopped after the target wheel loading is reached. The method alternatively includes selecting a target reflectivity of wafer grinding processes, and performing a grinding process on a wafer. With a proceeding of the grinding process, reflectivities of a light reflected from a surface of the wafer are measured. The grinding process is stopped after one of the reflectivities reaches the target reflectivity.

公开(公告)号：US09349655B2

公开(公告)日：2016-05-24

申请号：US12391821

申请日：2009-02-24

申请人： Carlos H. Diaz ,  Yi-Ming Sheu ,  Anson Wang ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Harry Hak-Lay Chuang ,  Shin-Puu Jeng

发明人： Carlos H. Diaz ,  Yi-Ming Sheu ,  Anson Wang ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Harry Hak-Lay Chuang ,  Shin-Puu Jeng

IPC分类号： H01L21/70 ,  H01L21/8238 ,  H01L27/02 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/823828 ,  H01L27/0207 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7848

摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having an active region; at least one operational device on the active region, wherein the operational device include a strained channel; and at least one first dummy gate disposed at a side of the operational device and on the active region.

摘要翻译： 本发明提供集成电路。 集成电路包括具有有源区的半导体衬底; 所述活动区域上的至少一个操作装置，其中所述操作装置包括应变通道; 以及设置在所述操作装置的一侧和所述有源区域上的至少一个第一伪栅极。

公开(公告)号：US09337123B2

公开(公告)日：2016-05-10

申请号：US13546218

申请日：2012-07-11

申请人： Cheng-Chieh Hsieh ,  Way Lee Cheng ,  Shang-Yun Hou ,  Shin-Puu Jeng

发明人： Cheng-Chieh Hsieh ,  Way Lee Cheng ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC分类号： H01L23/367 ,  H01L23/427 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00

CPC分类号： H01L23/427 ,  H01L21/563 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/562 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/06589

摘要： One or more heat pipes are utilized along with a substrate in order to provide heat dissipation through the substrate for heat that can build up at an interface between the substrate and one or more semiconductor chips in a package. In an embodiment the heat pipe may be positioned on a side of the substrate opposite the semiconductor chip and through-substrate vias may be utilized to dissipate heat through the substrate. In an alternative embodiment, the heat pipe may be positioned on a same side of the substrate as the semiconductor chip and may be thermally connected to the one or more semiconductor chips.

摘要翻译： 一个或多个热管与衬底一起使用，以便提供通过衬底的热量，其可以在衬底和封装中的一个或多个半导体芯片之间的界面处积聚。 在一个实施例中，热管可以位于与半导体芯片相对的一侧的衬底上，并且通孔衬底可以用于通过衬底散热。 在替代实施例中，热管可以位于与半导体芯片相同的衬底侧上，并且可以热连接到一个或多个半导体芯片。

公开(公告)号：US20140042612A1

公开(公告)日：2014-02-13

申请号：US13569017

申请日：2012-08-07

申请人： Christianto Chih-Ching Liu ,  Shuo-Mao Chen ,  Der-Chyang Yeh ,  Shang-Yun Hou ,  Shin-Puu Jeng

发明人： Christianto Chih-Ching Liu ,  Shuo-Mao Chen ,  Der-Chyang Yeh ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC分类号： H01L23/48 ,  H01L21/02

CPC分类号： H01L23/5226 ,  H01L21/76807 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2924/0002 ,  H05K1/0215 ,  H01L2924/00

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In an embodiment, a method of manufacturing a semiconductor device includes forming a first conductive structure over a workpiece in a first metallization layer, the first conductive structure including a first portion having a first width and a second portion having a second width. The second width is different than the first width. The method includes forming a second conductive structure in a second metallization layer proximate the first metallization layer, and coupling a portion of the second conductive structure to the first portion of the first conductive structure.

摘要翻译： 公开了半导体器件及其制造方法。 在一个实施例中，制造半导体器件的方法包括在第一金属化层中在工件上形成第一导电结构，第一导电结构包括具有第一宽度的第一部分和具有第二宽度的第二部分。 第二宽度与第一宽度不同。 该方法包括在靠近第一金属化层的第二金属化层中形成第二导电结构，以及将第二导电结构的一部分耦合到第一导电结构的第一部分。

公开(公告)号：US08643147B2

公开(公告)日：2014-02-04

申请号：US11933931

申请日：2007-11-01

申请人： Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Chen-Hua Yu

发明人： Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Chen-Hua Yu

IPC分类号： H01L23/544

CPC分类号： H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a lower dielectric layer; an upper dielectric layer over the lower dielectric layer; and a seal ring. The seal ring includes an upper metal line in the upper dielectric layer; a continuous via bar underlying and abutting the upper metal line, wherein the continuous via bar has a width greater than about 70 percent of a width of the upper metal line; a lower metal line in the lower dielectric layer; and a via bar underlying and abutting the lower metal line. The via bar has a width substantially less than a half of a width of the lower metal line.

摘要翻译： 集成电路结构包括下介电层; 在下介电层上的上电介质层; 和密封环。 密封环包括在上介电层中的上金属线; 连续的通孔条，其下面并邻接上部金属线，其中所述连续通孔条具有大于所述上部金属线宽度的约70％的宽度; 下介电层中的下金属线; 以及位于下金属线下方并邻接的通孔条。 通孔棒具有基本上小于下金属线宽度的一半的宽度。

公开(公告)号：US08558229B2

公开(公告)日：2013-10-15

申请号：US13313747

申请日：2011-12-07

申请人： Shin-Puu Jeng ,  Wei-Cheng Wu ,  Shang-Yun Hou ,  Chen-Hua Yu ,  Tzuan-Horng Liu ,  Tzu-Wei Chiu ,  Kuo-Ching Hsu

发明人： Shin-Puu Jeng ,  Wei-Cheng Wu ,  Shang-Yun Hou ,  Chen-Hua Yu ,  Tzuan-Horng Liu ,  Tzu-Wei Chiu ,  Kuo-Ching Hsu

IPC分类号： H01L23/58

CPC分类号： H01L22/34 ,  G01R31/2884 ,  H01L21/76885 ,  H01L22/32 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02126 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/10126 ,  H01L2224/13005 ,  H01L2224/16225 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/00

摘要： The embodiments described above provide mechanisms for forming metal bumps on metal pads with testing pads on a packaged integrated circuit (IC) chip. A passivation layer is formed to cover the testing pads and possibly portions of metal pads. The passivation layer does not cover surfaces away from the testing pad region and the metal pad region. The limited covering of the testing pads and the portions of the metal pads by the passivation layer reduces interface resistance for a UBM layer formed between the metal pads and the metal bumps. Such reduction of interface resistance leads to the reduction of resistance of the metal bumps.

摘要翻译： 上述实施例提供了在封装的集成电路（IC）芯片上用测试焊盘在金属焊盘上形成金属凸块的机构。 形成钝化层以覆盖测试焊盘和可能的金属焊盘部分。 钝化层不覆盖远离测试焊盘区域和金属焊盘区域的表面。 通过钝化层测试焊盘和金属焊盘部分的有限覆盖减少了形成在金属焊盘和金属凸块之间的UBM层的界面电阻。 这种界面电阻的降低导致金属凸块的电阻降低。

公开(公告)号：US20130087951A1

公开(公告)日：2013-04-11

申请号：US13270957

申请日：2011-10-11

申请人： Jing-Cheng Lin ,  Hsien-Wen Liu ,  Jui-Pin Hung ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Jing-Cheng Lin ,  Hsien-Wen Liu ,  Jui-Pin Hung ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H05B6/64 ,  B29C35/08

CPC分类号： B29C35/0805 ,  B29C2035/0855 ,  H01L21/565 ,  H05B6/6491 ,  H05B6/806

摘要： An embodiment is a molding chamber. The molding chamber comprises a mold-conforming chase, a substrate-base chase, a first radiation permissive component, and a microwave generator coupled to a first waveguide. The mold-conforming chase is over the substrate-base chase, and the mold-conforming chase is moveable in relation to the substrate-base chase. The first radiation permissive component is in one of the mold-conforming chase or the substrate-base chase. The microwave generator and the first waveguide are together operable to direct microwave radiation through the first radiation permissive component.

公开(公告)号：US20130087908A1

公开(公告)日：2013-04-11

申请号：US13267200

申请日：2011-10-06

申请人： Chen-Hua YU ,  Hung-Pin CHANG ,  An-Jhih SU ,  Tsang-Jiuh WU ,  Wen-Chih CHIOU ,  Shin-Puu JENG

发明人： Chen-Hua YU ,  Hung-Pin CHANG ,  An-Jhih SU ,  Tsang-Jiuh WU ,  Wen-Chih CHIOU ,  Shin-Puu JENG

IPC分类号： H01L23/498

CPC分类号： H01L23/293 ,  H01L23/3192 ,  H01L24/01 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/04941 ,  H01L2924/01047 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device includes a bump structure formed on a post-passivation interconnect (PPI) line and surrounded by a protection structure. The protection structure includes a polymer layer and at least one dielectric layer. The dielectric layer may be formed on the top surface of the polymer layer, underlying the polymer layer, inserted between the bump structure and the polymer layer, inserted between the PPI line and the polymer layer, covering the exterior sidewalls of the polymer layer, or combinations thereof.

摘要翻译： 半导体器件包括形成在钝化后互连（PPI）线上并由保护结构包围的凸块结构。 保护结构包括聚合物层和至少一个电介质层。 电介质层可以形成在聚合物层的顶表面上，该聚合物层的下面，插入凸起结构和聚合物层之间，插入在PPI线和聚合物层之间，覆盖聚合物层的外侧壁，或 其组合。

公开(公告)号：US20130075892A1

公开(公告)日：2013-03-28

申请号：US13246553

申请日：2011-09-27

申请人： Jing-Cheng Lin ,  Weng-Jin Wu ,  Ying-Ching Shih ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Jing-Cheng Lin ,  Weng-Jin Wu ,  Ying-Ching Shih ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L23/48 ,  H01L21/6835 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/83

摘要： A method for fabricating three dimensional integrated circuits comprises providing a wafer stack wherein a plurality of semiconductor dies are mounted on a first semiconductor die, forming a molding compound layer on the first side of the first semiconductor die, wherein the plurality of semiconductor dies are embedded in the molding compound layer. The method further comprises grinding a second side of the first semiconductor die until a plurality of through vias become exposed, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.

摘要翻译： 一种用于制造三维集成电路的方法包括：提供其中多个半导体管芯安装在第一半导体管芯上的晶片堆叠，在第一半导体管芯的第一侧上形成模塑料层，其中多个半导体管芯被嵌入 在模塑料层中。 该方法还包括研磨第一半导体管芯的第二面直到多个通孔露出，将晶片堆叠附着到带框架上并切割晶片堆叠以将晶片堆叠分离成多个单独的封装。

公开(公告)号：US20130001776A1

公开(公告)日：2013-01-03

申请号：US13170973

申请日：2011-06-28

申请人： Chen-Hua Yu ,  Jing-Cheng Lin ,  Nai-Wei Liu ,  Jui-Pin Hung ,  Shin-Puu Jeng

发明人： Chen-Hua Yu ,  Jing-Cheng Lin ,  Nai-Wei Liu ,  Jui-Pin Hung ,  Shin-Puu Jeng

IPC分类号： H01L23/485 ,  H01L21/28

CPC分类号： H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/214

摘要： A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.

摘要翻译： 封装包括具有基板的器件裸片。 模塑料与基材的侧壁接触。 金属焊盘在基板上。 钝化层具有覆盖金属焊盘的边缘部分的部分。 金属支柱已经过去并与金属垫接触。 介电层位于钝化层的上方。 由模塑料或聚合物形成的包装材料在电介质层的上面。 电介质层包括位于钝化层和封装材料之间的底部，以及在金属柱的侧壁和封装材料的侧壁之间的侧壁部分。 聚合物层在包装材料，模塑料和金属支柱之上。 后钝化互连（PPI）延伸到聚合物层中。 焊球在PPI上方，并通过PPI电耦合到金属焊盘。