公开(公告)号：US09620421B2

公开(公告)日：2017-04-11

申请号：US12948184

申请日：2010-11-17

申请人： Chien-Chih Ho ,  Chih-Ping Chao ,  Hua-Chou Tseng ,  Chun-Hung Chen ,  Chia-Yi Su ,  Alex Kalnitsky ,  Jye-Yen Cheng ,  Harry-Hak-Lay Chuang

发明人： Chien-Chih Ho ,  Chih-Ping Chao ,  Hua-Chou Tseng ,  Chun-Hung Chen ,  Chia-Yi Su ,  Alex Kalnitsky ,  Jye-Yen Cheng ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/8238 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L23/481 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

摘要： A method of forming an integrated circuit structure includes providing a gate strip in an inter-layer dielectric (ILD) layer. The gate strip comprises a metal gate electrode over a high-k gate dielectric. An electrical transmission structure is formed over the gate strip and a conductive strip is formed over the electrical transmission structure. The conductive strip has a width greater than a width of the gate strip. A contact plug is formed above the conductive strip and surrounded by an additional ILD layer.

公开(公告)号：US09595443B2

公开(公告)日：2017-03-14

申请号：US13277642

申请日：2011-10-20

申请人： Ming Zhu ,  Hui-Wen Lin ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Yuan-Sheng Huang ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen ,  Kuo-Cheng Ching ,  Ting-Hua Hsieh ,  Carlos H. Diaz

发明人： Ming Zhu ,  Hui-Wen Lin ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Yuan-Sheng Huang ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen ,  Kuo-Cheng Ching ,  Ting-Hua Hsieh ,  Carlos H. Diaz

IPC分类号： H01L21/70 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/42376 ,  H01L29/4966

摘要： The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising an isolation region surrounding and separating a P-active region and an N-active region; a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region.

摘要翻译： 本发明涉及集成电路制造，更具体地涉及一种金属栅极结构。 CMOS半导体器件的示例性结构包括：衬底，包括围绕并分离P活性区域和N-有源区域的隔离区域; 在P-活性区域上的P金属栅电极，并且在隔离区域上延伸，其中P金属栅电极包括P功函数金属和P功函数金属与衬底之间的含氧TiN层; 以及N型金属栅电极，其在N-有源区上方并在隔离区上方延伸，其中N型金属栅电极包括N功函数金属和N功函数金属与衬底之间的富氮TiN层 其中富氮TiN层在隔离区域上连接到含氧TiN层。

公开(公告)号：US09070784B2

公开(公告)日：2015-06-30

申请号：US13189232

申请日：2011-07-22

申请人： Ming Zhu ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

发明人： Ming Zhu ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

IPC分类号： H01L21/338 ,  H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/3212 ,  H01L21/82385 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/0642

摘要： The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate, an N-metal gate electrode, and a P-metal gate electrode. The substrate comprises an isolation region surrounding a P-active region and an N-active region. The N-metal gate electrode comprises a first metal composition over the N-active region. The P-metal gate electrode comprises a bulk portion over the P-active region and an endcap portion over the isolation region. The endcap portion comprises the first metal composition and the bulk portion comprises a second metal composition different from the first metal composition.

摘要翻译： 本发明涉及集成电路制造，更具体地涉及一种金属栅极结构。 CMOS半导体器件的示例性结构包括衬底，N金属栅电极和P金属栅电极。 衬底包括围绕P活性区域和N-活性区域的隔离区域。 所述N-金属栅电极包括在所述N-活性区上的第一金属组合物。 P型金属栅电极包括位于P有源区上的本体部分和在隔离区上方的端盖部分。 端盖部分包括第一金属组合物，并且本体部分包含不同于第一金属组合物的第二金属组合物。

公开(公告)号：US09070623B2

公开(公告)日：2015-06-30

申请号：US12897559

申请日：2010-10-04

申请人： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Kuei Shun Chen ,  Cheng Cheng Kuo ,  George Liu ,  Tsung-Chieh Tsai ,  Yuhi-Jier Mii

发明人： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Kuei Shun Chen ,  Cheng Cheng Kuo ,  George Liu ,  Tsung-Chieh Tsai ,  Yuhi-Jier Mii

IPC分类号： H01L21/338 ,  H01L21/28 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L21/28123 ,  H01L21/823437 ,  H01L27/0207 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7831

摘要： Methods of forming a semiconductor structure and the semiconductor structure are disclosed. In one embodiment, a method includes forming a gate dielectric layer over a substrate, forming a gate electrode layer over the gate dielectric layer, and etching the gate electrode layer and the gate dielectric layer to form a horizontal gate structure and a vertical gate structure, wherein the horizontal gate structure and the vertical gate structure are connected by an interconnection portion. The method further includes forming a photoresist covering the horizontal gate structure and the vertical gate structure, with the photoresist having a gap exposing the interconnection portion between the horizontal gate structure and the vertical gate structure, and then etching the interconnection portion.

摘要翻译： 公开了形成半导体结构和半导体结构的方法。 在一个实施例中，一种方法包括在衬底上形成栅极电介质层，在栅极电介质层上形成栅极电极层，并蚀刻栅极电极层和栅极电介质层以形成水平栅极结构和垂直栅极结构， 其中所述水平栅极结构和所述垂直栅极结构通过互连部分连接。 该方法还包括形成覆盖水平栅极结构和垂直栅极结构的光致抗蚀剂，其中光致抗蚀剂具有暴露水平栅极结构和垂直栅极结构之间的互连部分的间隙，然后蚀刻互连部分。

公开(公告)号：US08835294B2

公开(公告)日：2014-09-16

申请号：US12724984

申请日：2010-03-16

申请人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry Hak-Lay Chuang ,  Yi-Ren Chen

发明人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry Hak-Lay Chuang ,  Yi-Ren Chen

IPC分类号： H01L21/3205 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3215 ,  H01L29/49 ,  H01L21/768 ,  H01L21/8238

CPC分类号： H01L21/28088 ,  H01L21/02697 ,  H01L21/3215 ,  H01L21/76825 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545

摘要： The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure on the substrate, the gate structure including a dummy gate, removing the dummy gate from the gate structure thereby forming a trench, forming a work function metal layer partially filling the trench, forming a fill metal layer filling a remainder of the trench, performing a chemical mechanical polishing (CMP) to remove portions of the metal layers outside the trench, and implanting Si, C, or Ge into a remaining portion of the fill metal layer.

摘要翻译： 本公开提供了一种制造半导体器件的方法，该半导体器件包括提供半导体衬底，在衬底上形成栅极结构，所述栅极结构包括虚拟栅极，从栅极结构去除伪栅极，从而形成沟槽，形成工件 功能金属层部分地填充沟槽，形成填充沟槽的其余部分的填充金属层，执行化学机械抛光（CMP）以去除沟槽外部的金属层，并将Si，C或Ge注入剩余的 填充金属层的一部分。

公开(公告)号：US08697517B2

公开(公告)日：2014-04-15

申请号：US12724904

申请日：2010-03-16

申请人： Harry Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo

发明人： Harry Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo

IPC分类号： H01L21/8242

CPC分类号： H01L27/0617 ,  H01L23/5227 ,  H01L27/0207 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides reduced substrate coupling for inductors in semiconductor devices. A method of fabricating a semiconductor device having reduced substrate coupling includes providing a substrate having a first region and a second region. The method also includes forming a first gate structure over the first region and a second gate structure over the second region, wherein the first and second gate structures each include a dummy gate. The method next includes forming an inter layer dielectric (ILD) over the substrate and forming a photoresist (PR) layer over the second gate structure. Then, the method includes removing the dummy gate from the first gate structure, thereby forming a trench and forming a metal gate in the trench so that a transistor may be formed in the first region, which includes a metal gate, and an inductor component may be formed over the second region, which does not include a metal gate.

摘要翻译： 本公开为半导体器件中的电感器提供了减少的衬底耦合。 制造具有减小的衬底耦合的半导体器件的方法包括提供具有第一区域和第二区域的衬底。 该方法还包括在第一区域上形成第一栅极结构，在第二区域上形成第二栅极结构，其中第一和第二栅极结构各自包括虚拟栅极。 该方法接下来包括在衬底上形成层间电介质（ILD），并在第二栅极结构上形成光致抗蚀剂（PR）层。 然后，该方法包括从第一栅极结构中去除伪栅极，由此形成沟槽并在沟槽中形成金属栅极，使得晶体管可以形成在包括金属栅极的第一区域中，并且电感器元件可以 形成在不包括金属栅极的第二区域上。

公开(公告)号：US08664079B2

公开(公告)日：2014-03-04

申请号：US13316817

申请日：2011-12-12

申请人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry-Hak-Lay Chuang

发明人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/76

CPC分类号： H01L21/3081 ,  H01L21/76232

摘要： The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate.

摘要翻译： 本公开涉及集成电路制造，更具体地涉及一种用于制造半导体器件的方法。 用于制造半导体器件的示例性方法包括提供衬底; 在衬底的前侧和后侧形成衬垫氧化物层; 在衬底的前侧和后侧上的衬垫氧化物层上形成硬掩模层; 以及在衬底的前侧的衬垫氧化物层之上使硬掩模层变薄。

公开(公告)号：US08525270B2

公开(公告)日：2013-09-03

申请号：US12713395

申请日：2010-02-26

申请人： Lee-Wee Teo ,  Ming Zhu ,  Chi-Ju Lee ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Harry-Hak-Lay Chuang

发明人： Lee-Wee Teo ,  Ming Zhu ,  Chi-Ju Lee ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/70

CPC分类号： H01L29/66545 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/78

摘要： The methods and structures described are used to prevent protrusion of contact metal (such as W) horizontally into gate stacks of neighboring devices to affect the work functions of these neighboring devices. The metal gate under contact plugs that are adjacent to devices and share the (or are connected to) metal gate is defined and lined with a work function layer that has good step coverage to prevent contact metal from extruding into gate stacks of neighboring devices. Only modification to the mask layout for the photomask(s) used for removing dummy polysilicon is involved. No additional lithographical operation or mask is needed. Therefore, no modification to the manufacturing processes or additional substrate processing steps (or operations) is involved or required. The benefits of using the methods and structures described above may include increased device yield and performance.

摘要翻译： 所描述的方法和结构用于防止接触金属（例如W）水平地突出到相邻设备的门堆叠中，以影响这些相邻设备的功能。 定义了与设备相邻并且共享（或连接到）金属栅极的接触插塞下面的金属栅，并且衬有具有良好阶梯覆盖的功函数层，以防止接触金属挤出到相邻器件的栅极堆叠中。 仅涉及用于去除伪多晶硅的光掩模的掩模布局的修改。 不需要额外的光刻操作或掩模。 因此，不涉及制造工艺或附加的基板处理步骤（或操作）的修改。 使用上述方法和结构的好处可以包括提高器件产量和性能。

公开(公告)号：US08524570B2

公开(公告)日：2013-09-03

申请号：US12890995

申请日：2010-09-27

申请人： Harry Hak-Lay Chuang ,  Chih-Yang Yeh ,  Bao-Ru Young ,  Yuh-Jier Mii

发明人： Harry Hak-Lay Chuang ,  Chih-Yang Yeh ,  Bao-Ru Young ,  Yuh-Jier Mii

IPC分类号： H01L21/76

CPC分类号： H01L29/78 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823456 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088

摘要： A method of fabricating a semiconductor device includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface disposed below the first surface, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface disposed below the first surface, a gate structure, and a contact engaging the gate structure over the recess.

摘要翻译： 一种制造半导体器件的方法包括提供具有第一表面的衬底，形成部分地设置在衬底中的隔离结构，并且具有高于第一表面的第二表面，台阶高度，去除隔离结构的一部分以形成 在其中具有设置在第一表面下方的底表面的凹槽，以及形成在凹部上方接合栅极结构的触点。 不同的方面涉及一种装置，其包括具有第一表面的衬底，部分地设置在衬底中的隔离结构，并且具有比第一表面高的台阶高度的第二表面;从第二表面向下延伸的凹部，凹部具有 设置在第一表面下方的底表面，栅极结构，以及在凹部上接合栅极结构的触点。

公开(公告)号：US08450834B2

公开(公告)日：2013-05-28

申请号：US12706191

申请日：2010-02-16

申请人： Jin-Aun Ng ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang ,  Ryan Chia-Jen Chen

发明人： Jin-Aun Ng ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang ,  Ryan Chia-Jen Chen

IPC分类号： H01L21/8238

CPC分类号： H01L29/401 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

摘要： This disclosure relates to a spacer structure of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate structure that has a sidewall overlying the substrate; a silicide region in the substrate on one side of the gate structure having an inner edge closest to the gate structure; a first oxygen-sealing layer adjoining the sidewall of the gate structure; an oxygen-containing layer adjoining the first oxygen-sealing layer on the sidewall and further including a portion extending over the substrate; and a second oxygen-sealing layer adjoining the oxygen-containing layer and extending over the portion of the oxygen-containing layer over the substrate, wherein an outer edge of the second oxygen-sealing layer is offset from the inner edge of the silicide region.

摘要翻译： 本公开涉及场效应晶体管的间隔结构。 场效应晶体管的示例性结构包括：衬底; 栅极结构，其具有覆盖所述衬底的侧壁; 所述栅极结构的一侧上的所述衬底中的硅化物区域具有最靠近所述栅极结构的内部边缘; 与栅极结构的侧壁相邻的第一氧气密封层; 邻接所述侧壁上的所述第一氧气密封层并且还包括在所述衬底上延伸的部分的含氧层; 以及邻接所述含氧层并在所述基底上的所述含氧层的所述部分上延伸的第二氧气密封层，其中所述第二氧气密封层的外边缘从所述硅化物区域的内边缘偏移。