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    Metal gate structure of a CMOS semiconductor device and method of forming the same
    2.
    发明授权
    Metal gate structure of a CMOS semiconductor device and method of forming the same 有权
    CMOS半导体器件的金属栅极结构及其形成方法

    公开(公告)号：US09070784B2

    公开(公告)日：2015-06-30

    申请号：US13189232

    申请日：2011-07-22

    申请人： Ming Zhu ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

    发明人： Ming Zhu ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

    IPC分类号： H01L21/338 ,  H01L21/8238

    CPC分类号： H01L21/823814 ,  H01L21/3212 ,  H01L21/82385 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/0642

    摘要： The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate, an N-metal gate electrode, and a P-metal gate electrode. The substrate comprises an isolation region surrounding a P-active region and an N-active region. The N-metal gate electrode comprises a first metal composition over the N-active region. The P-metal gate electrode comprises a bulk portion over the P-active region and an endcap portion over the isolation region. The endcap portion comprises the first metal composition and the bulk portion comprises a second metal composition different from the first metal composition.

    摘要翻译： 本发明涉及集成电路制造，更具体地涉及一种金属栅极结构。 CMOS半导体器件的示例性结构包括衬底，N金属栅电极和P金属栅电极。 衬底包括围绕P活性区域和N-活性区域的隔离区域。 所述N-金属栅电极包括在所述N-活性区上的第一金属组合物。 P型金属栅电极包括位于P有源区上的本体部分和在隔离区上方的端盖部分。 端盖部分包括第一金属组合物，并且本体部分包含不同于第一金属组合物的第二金属组合物。

    Spacer structures of a semiconductor device
    3.
    发明授权
    Spacer structures of a semiconductor device 有权
    半导体器件的间隔结构

    公开(公告)号：US08304840B2

    公开(公告)日：2012-11-06

    申请号：US12846261

    申请日：2010-07-29

    申请人： Lee-Wee Teo ,  Ming Zhu ,  Hui-Wen Lin ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

    发明人： Lee-Wee Teo ,  Ming Zhu ,  Hui-Wen Lin ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

    IPC分类号： H01L21/02 ,  H01L21/70 ,  H01L27/088

    CPC分类号： H01L29/401 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088

    摘要： The disclosure relates to spacer structures of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate having a first active region and a second active region; a plurality of first gate electrodes having a gate pitch over the first active region, wherein each first gate electrode has a first width; a plurality of first spacers adjoining the plurality of first gate electrodes, wherein each first spacer has a third width; a plurality of second gate electrodes having the same gate pitch as the plurality of first gate electrodes over the second active region, wherein each second gate electrode has a second width greater than the first width; and a plurality of second spacers adjoining the plurality of second gate electrodes, wherein each second spacer has a fourth width less than the third width.

    摘要翻译： 本公开涉及半导体器件的间隔结构。 半导体器件的示例性结构包括具有第一有源区和第二有源区的衬底; 多个在所述第一有源区上具有栅间距的第一栅电极，其中每个第一栅电极具有第一宽度; 与所述多个第一栅电极相邻的多个第一间隔件，其中每个第一间隔件具有第三宽度; 多个第二栅电极，其具有与第二有源区上的多个第一栅电极相同的栅极间距，其中每个第二栅电极具有大于第一宽度的第二宽度; 以及与所述多个第二栅电极相邻的多个第二间隔件，其中每个第二间隔件具有小于所述第三宽度的第四宽度。

    Metal gate structure of a CMOS semiconductor device
    4.
    发明授权
    Metal gate structure of a CMOS semiconductor device 有权
    CMOS半导体器件的金属栅极结构

    公开(公告)号：US08183644B1

    公开(公告)日：2012-05-22

    申请号：US13025956

    申请日：2011-02-11

    申请人： Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Ming Zhu ,  Hui-Wen Lin ,  Lee-Wee Teo

    发明人： Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Ming Zhu ,  Hui-Wen Lin ,  Lee-Wee Teo

    IPC分类号： H01L21/027

    CPC分类号： H01L21/823842 ,  H01L21/823871

    摘要： The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising a P-active region, an N-active region, and an isolation region interposed between the P- and N-active regions; a P-metal gate electrode over the P-active region, that extends over the isolation region; and an N-metal gate electrode having a first width over the N-active region, that extends over the isolation region and has a contact section in the isolation region electrically contacting the P-metal gate electrode, wherein the contact section has a second width greater than the first width.

    摘要翻译： 本发明涉及集成电路制造，更具体地涉及一种金属栅极结构。 CMOS半导体器件的示例性结构包括：衬底，其包括P活性区域，N活性区域和插入在P-活性区域和N - 活性区域之间的隔离区域; 在P-活性区域上的P金属栅极电极，其在隔离区域上延伸; 以及在所述N-有源区上具有第一宽度的N-金属栅电极，其在所述隔离区上延伸，并且在所述隔离区中具有与所述P金属栅电极电接触的接触部，其中所述接触部具有第二宽度 大于第一宽度。

    METHOD AND APPARATUS FOR IMPROVING GATE CONTACT
    5.
    发明申请
    METHOD AND APPARATUS FOR IMPROVING GATE CONTACT 有权
    改善门接触的方法和装置

    公开(公告)号：US20120001259A1

    公开(公告)日：2012-01-05

    申请号：US12830107

    申请日：2010-07-02

    申请人： Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Jin-Aun Ng ,  Wei Cheng Wu ,  Ming Zhu

    发明人： Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Jin-Aun Ng ,  Wei Cheng Wu ,  Ming Zhu

    IPC分类号： H01L29/772 ,  H01L21/28

    CPC分类号： H01L21/823481 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L29/66545

    摘要： A method includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface spaced from the first surface by less than the step height, forming a gate structure, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface spaced from the first surface by less than the step height, a gate structure, and a contact engaging the gate structure over the recess.

    摘要翻译： 一种方法包括提供具有第一表面的基板，形成部分地设置在基板中的隔离结构，并且具有高于第一表面的台阶高度的第二表面，去除隔离结构的一部分以形成其中具有底部 表面与所述第一表面间隔开小于所述台阶高度，形成栅极结构，以及形成在所述凹部上接合所述栅极结构的触点。 不同的方面涉及一种装置，其包括具有第一表面的衬底，部分地设置在衬底中的隔离结构，并且具有比第一表面高的台阶高度的第二表面;从第二表面向下延伸的凹部，凹部具有 与所述第一表面间隔小于所述台阶高度的底表面，栅极结构以及在所述凹部上接合所述栅极结构的触点。

    Metal gate structure of a semiconductor device
    6.
    发明授权
    Metal gate structure of a semiconductor device 有权
    半导体器件的金属栅极结构

    公开(公告)号：US08378428B2

    公开(公告)日：2013-02-19

    申请号：US12893338

    申请日：2010-09-29

    申请人： Han-Guan Chew ,  Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

    发明人： Han-Guan Chew ,  Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

    IPC分类号： H01L21/02

    CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/82385 ,  H01L29/66545

    摘要： The applications discloses a semiconductor device comprising a substrate having a first active region, a second active region, and an isolation region having a first width interposed between the first and second active regions; a P-metal gate electrode over the first active region and extending over at least ⅔ of the first width of the isolation region; and an N-metal gate electrode over the second active region and extending over no more than ⅓ of the first width. The N-metal gate electrode is electrically connected to the P-metal gate electrode over the isolation region.

    摘要翻译： 应用公开了一种半导体器件，其包括具有第一有源区，第二有源区和具有介于第一和第二有源区之间的第一宽度的隔离区的衬底; 在所述第一有源区上方的P金属栅电极，并且延伸至所述隔离区的第一宽度的至少;; 以及在第二有源区上方的N极金属栅电极，并延伸超过第一宽度的1/3。 N型金属栅电极在隔离区域上电连接到P金属栅电极。

    OFFSET GATE SEMICONDUCTOR DEVICE
    9.
    发明申请
    OFFSET GATE SEMICONDUCTOR DEVICE 有权
    偏移栅极半导体器件

    公开(公告)号：US20120025309A1

    公开(公告)日：2012-02-02

    申请号：US12846457

    申请日：2010-07-29

    申请人： Chun-Hung Chen ,  Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

    发明人： Chun-Hung Chen ,  Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L29/513 ,  H01L29/495

    摘要： An offset gate semiconductor device includes a substrate and an isolation feature formed in the substrate. An active region is formed in the substrate substantially adjacent to the isolation feature. An interface layer is formed on the substrate over the isolation feature and the active region. A polysilicon layer is formed on the interface layer over the isolation feature and the active region. A trench being formed in the polysilicon layer over the isolation feature. The trench extending to the interface layer. A fill layer is formed to line the trench and a metal gate formed in the trench.

    摘要翻译： 偏移门半导体器件包括衬底和形成在衬底中的隔离特征。 在基板上基本上与隔离特征相邻地形成有源区。 在隔离特征和有源区上的衬底上形成界面层。 在隔离特征和有源区上的界面层上形成多晶硅层。 在隔离特征上形成在多晶硅层中的沟槽。 沟槽延伸到界面层。 形成填充层以在沟槽中形成沟槽和形成的金属栅极。