公开(公告)号：US09000533B2

公开(公告)日：2015-04-07

申请号：US13457079

申请日：2012-04-26

申请人： Wei Cheng Wu ,  Po-Nien Chen ,  Jin-Aun Ng ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

发明人： Wei Cheng Wu ,  Po-Nien Chen ,  Jin-Aun Ng ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

IPC分类号： H01L27/11 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/51

CPC分类号： H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0629 ,  H01L29/4925 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

摘要翻译： 描述了在基板的不同区域上具有五个栅极叠层的半导体器件及其制造方法。 该器件包括半导体衬底和用于分离衬底上的不同区域的隔离特征。 不同的区域包括p型场效应晶体管（pFET）芯区域，输入/输出pFET（pFET IO）区域，n型场效应晶体管（nFET）核心区域，输入/输出nFET（nFET） IO）区域和高电阻区域。

公开(公告)号：US08587074B2

公开(公告)日：2013-11-19

申请号：US13101727

申请日：2011-05-05

申请人： Harry-Hak-Lay Chuang ,  Ming-Hsiang Song ,  Kuo-Ji Chen ,  Ming Zhu ,  Po-Nien Chen ,  Bao-Ru Young

发明人： Harry-Hak-Lay Chuang ,  Ming-Hsiang Song ,  Kuo-Ji Chen ,  Ming Zhu ,  Po-Nien Chen ,  Bao-Ru Young

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/0266 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66666 ,  H01L29/66681 ,  H01L29/7835

摘要： A device includes a drain, a source, and a gate stack. The gate stack has a gate dielectric layer, a gate conductive layer immediately on top of the gate dielectric layer, and first gate and a second gate layer that are immediately on top of the gate conductive layer. The first gate layer has a first resistance higher than a second resistance of the second gate layer. The second gate layer is conductive, is electrically coupled with the gate conductive layer, and has a contact terminal configured to serve as a gate contact terminal for the device. Fabrication methods of the gate stack are also disclosed.

摘要翻译： 一种器件包括漏极，源极和栅极叠层。 栅极堆叠具有栅极电介质层，立即在栅极电介质层的顶部上的栅极导电层，以及立即在栅极导电层顶部上的第一栅极和第二栅极层。 第一栅极层具有比第二栅极层的第二电阻高的第一电阻。 第二栅极层是导电的，与栅极导电层电耦合，并且具有被配置为用作器件的栅极接触端子的接触端子。 还公开了栅极堆叠的制造方法。

公开(公告)号：US20130285150A1

公开(公告)日：2013-10-31

申请号：US13456939

申请日：2012-04-26

申请人： Po-Nien Chen ,  Jin-Aun Ng ,  Ming Zhu ,  Bao-Ru Young ,  Hak-Lay Chuang

发明人： Po-Nien Chen ,  Jin-Aun Ng ,  Ming Zhu ,  Bao-Ru Young ,  Hak-Lay Chuang

IPC分类号： H01L27/092 ,  H01L21/283

CPC分类号： H01L21/823842 ,  H01L21/28158 ,  H01L21/823857 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0653 ,  H01L29/4933 ,  H01L29/511 ,  H01L29/512 ,  H01L29/517 ,  H01L29/78

摘要： A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

公开(公告)号：US20100301633A1

公开(公告)日：2010-12-02

申请号：US12472703

申请日：2009-05-27

申请人： Po-Nien Chen

发明人： Po-Nien Chen

IPC分类号： B62D37/02

CPC分类号： B62D35/005 ,  B60J11/02 ,  B62D35/007 ,  Y02T10/82

摘要： A vehicular rear spoiler, which is integrated with the trunk lid of a vehicle, comprises an electronic display arranged on the rear side of the spoiler body and a reelable heat-insulation sun shade collected inside the spoiler body, whereby not only advertisement or messages can be presented on the electronic display, but also the heat-insulation sun shade can be extended to the front of the vehicle to protect the vehicle from sunshine, rain and snow.

摘要翻译： 与车辆的行李箱盖一体化的车辆后扰流板包括布置在扰流板主体的后侧的电子显示器和收集在扰流体内部的可卷绕的隔热遮阳板，由此不仅广告或消息可以 呈现在电子显示屏上，而且隔热遮阳板也可以延伸到车前，保护车辆免受阳光，雨雪的影响。

公开(公告)号：US08698252B2

公开(公告)日：2014-04-15

申请号：US13456939

申请日：2012-04-26

申请人： Po-Nien Chen ,  Jin-Aun Ng ,  Ming Zhu ,  Bao-Ru Young ,  Hak-Lay Chuang

发明人： Po-Nien Chen ,  Jin-Aun Ng ,  Ming Zhu ,  Bao-Ru Young ,  Hak-Lay Chuang

IPC分类号： H01L27/11

CPC分类号： H01L21/823842 ,  H01L21/28158 ,  H01L21/823857 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0653 ,  H01L29/4933 ,  H01L29/511 ,  H01L29/512 ,  H01L29/517 ,  H01L29/78

摘要： A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

摘要翻译： 描述了在基板的不同区域上具有五个栅极叠层的半导体器件及其制造方法。 该器件包括半导体衬底和用于分离衬底上的不同区域的隔离特征。 不同的区域包括p型场效应晶体管（pFET）芯区域，输入/输出pFET（pFET IO）区域，n型场效应晶体管（nFET）核心区域，输入/输出nFET（nFET） IO）区域和高电阻区域。

公开(公告)号：US09546349B2

公开(公告)日：2017-01-17

申请号：US13118990

申请日：2011-05-31

申请人： How Tseng ,  Jeng-Kuen Tsai ,  Keng-Liang Ou ,  Po-Nien Chen

发明人： How Tseng ,  Jeng-Kuen Tsai ,  Keng-Liang Ou ,  Po-Nien Chen

IPC分类号： C12M1/26 ,  C12N5/00 ,  C12M1/12

CPC分类号： C12M25/00 ,  C12M25/06 ,  C12M33/00 ,  C12N5/0068 ,  C12N2533/30 ,  C12N2533/40

摘要： The invention creates a support for cell culture and cell sheet detachment which has a substrate, whose surface is coated with a conjugate having a disulfide bond-containing amino acid as a spacer and a biopolymer enhancing cell attachment, migration or differentation. Unexpectedly, after being seeded on the support, the cells grow to form one or more layers of cell sheets and the cell sheets can be easily detached from the support by adding a reductant to cleave the disulfide bond. Accordingly, the invention provides a simple and non-toxic method for detachment of cell sheets.

摘要翻译： 本发明产生了细胞培养和细胞片剥离的支持物，其具有底物，其表面用具有二硫键的氨基酸作为间隔基的缀合物和生物聚合物增强细胞附着，迁移或分化而被涂覆。 出人意料的是，在接种在载体上之后，细胞生长形成一层或多层细胞片，通过加入还原剂以切割二硫键，可以容易地将细胞片从载体上分离出来。 因此，本发明提供了用于分离细胞片的简单且无毒的方法。

公开(公告)号：US09093559B2

公开(公告)日：2015-07-28

申请号：US13415967

申请日：2012-03-09

申请人： Jin-Aun Ng ,  Po-Nien Chen ,  Sheng-Chen Chung ,  Bao-Ru Young ,  Hak-Lay Chuang

发明人： Jin-Aun Ng ,  Po-Nien Chen ,  Sheng-Chen Chung ,  Bao-Ru Young ,  Hak-Lay Chuang

IPC分类号： H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A process fabricating a semiconductor device with a hybrid HK/metal gate stack fabrication is disclosed. The process includes providing a semiconductor substrate having a plurality of isolation features between a PFET region and a NFET region, and forming gate stacks on the semiconductor substrate. In the PFET region, the gate stack is formed as a HK/metal gate. In the NFET region, the gate stack is formed as a polysilicon gate. A high-resistor is also formed on the semiconductor substrate by utilizing another polysilicon gate.

摘要翻译： 公开了一种制造具有混合HK /金属栅极堆叠制造的半导体器件的工艺。 该方法包括提供在PFET区域和NFET区域之间具有多个隔离特征的半导体衬底，以及在半导体衬底上形成栅叠层。 在PFET区域中，栅极堆叠形成为HK /金属栅极。 在NFET区域中，栅堆叠形成为多晶硅栅极。 通过利用另一个多晶硅栅极也在半导体衬底上形成高电阻。

公开(公告)号：US20130285151A1

公开(公告)日：2013-10-31

申请号：US13457079

申请日：2012-04-26

申请人： Wei Cheng Wu ,  Po-Nien Chen ,  Jin-Aun Ng ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

发明人： Wei Cheng Wu ,  Po-Nien Chen ,  Jin-Aun Ng ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

IPC分类号： H01L27/092 ,  H01L21/336

CPC分类号： H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0629 ,  H01L29/4925 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

公开(公告)号：US20130032884A1

公开(公告)日：2013-02-07

申请号：US13195628

申请日：2011-08-01

申请人： Hak-Lay Chuang ,  Ming Zhu ,  Po-Nien Chen ,  Bao-Ru Young

发明人： Hak-Lay Chuang ,  Ming Zhu ,  Po-Nien Chen ,  Bao-Ru Young

IPC分类号： H01L27/088 ,  G06F17/50 ,  H01L21/336

CPC分类号： H01L29/42376 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/0218 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/785 ,  H01L2223/58

摘要： A device, and method of fabricating and/or designing such a device, including a first gate structure having a width (W) and a length (L) and a second gate structure separated from the first gate structure by a distance greater than: (√{square root over (W*W+L*L)})/10. The second gate structure is a next adjacent gate structure to the first gate structure. A method and apparatus for designing an integrated circuit including implementing a design rule defining the separation of gate structures is also described. In embodiments, the distance of separation is implemented for gate structures that are larger relative to other gate structures on the substrate (e.g., greater than 3 μm2).

摘要翻译： 一种器件，以及制造和/或设计这种器件的方法，包括具有宽度（W）和长度（L）的第一栅极结构以及与第一栅极结构分离大于的距离的第二栅极结构： √{平方根（W * W + L * L）}）/ 10。 第二栅极结构是与第一栅极结构相邻的下一个栅极结构。 还描述了一种用于设计集成电路的方法和装置，包括实现限定栅极结构分离的设计规则。 在实施例中，对于相对于衬底上的其它栅极结构（例如，大于3μm2）较大的栅极结构，实现分离距离。

公开(公告)号：US20120280323A1

公开(公告)日：2012-11-08

申请号：US13101727

申请日：2011-05-05

申请人： Harry-Hak-Lay CHUANG ,  Ming-Hsiang SONG ,  Kuo-Ji CHEN ,  Ming ZHU ,  Po-Nien CHEN ,  Bao-Ru YOUNG

发明人： Harry-Hak-Lay CHUANG ,  Ming-Hsiang SONG ,  Kuo-Ji CHEN ,  Ming ZHU ,  Po-Nien CHEN ,  Bao-Ru YOUNG

IPC分类号： H01L27/092 ,  H01L29/772 ,  H01L21/28

CPC分类号： H01L27/0266 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66666 ,  H01L29/66681 ,  H01L29/7835

摘要： A device includes a drain, a source, and a gate stack. The gate stack has a gate dielectric layer, a gate conductive layer immediately on top of the gate dielectric layer, and first gate and a second gate layer that are immediately on top of the gate conductive layer. The first gate layer has a first resistance higher than a second resistance of the second gate layer. The second gate layer is conductive, is electrically coupled with the gate conductive layer, and has a contact terminal configured to serve as a gate contact terminal for the device. Fabrication methods of the gate stack are also disclosed.

摘要翻译： 一种器件包括漏极，源极和栅极叠层。 栅极堆叠具有栅极电介质层，立即在栅极电介质层的顶部上的栅极导电层，以及立即在栅极导电层顶部上的第一栅极和第二栅极层。 第一栅极层具有比第二栅极层的第二电阻高的第一电阻。 第二栅极层是导电的，与栅极导电层电耦合，并且具有被配置为用作器件的栅极接触端子的接触端子。 还公开了栅极堆叠的制造方法。